DAC5689 Datasheet, PDF (31/48 Pages) Texas Instruments – 16-BIT 800 MSPS 2x-8x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5689
www.ti.com .......................................................................................................................................................................................... SLLS989 – SEPTEMBER 2009
DUAL SYNCHRONOUS CLOCK MODE
In DUAL SYNCHRONOUS CLOCK MODE, the user provides the CLK2/C clock signal at the DAC sample rate
and also provides a divided down CLK1 at the input data rate. Refer to Figure 28 for the timing diagram. In this
mode the relationship between CLK2 and CLK1 (t_{_align}) is critical and used as a synchronizing mechanism for the
internal logic. This facilitates multi-DAC synchronization by using dual external clock inputs CLK1 and CLK2
while FIFO data is always written and read from location zero. It is highly recommended that a clock
synchronizer device such as the CDCM7005 provide both CLK2/C and CLK1/C inputs. Although CLK1 could be
single-ended it is recommended to use a differential clock to ensure proper skews between the two clock inputs.
DUAL CLOCK MODE
In DUAL CLOCK MODE, the user provides the CLK2/C clock signal at the DAC sample rate and also provides a
divided down CLK1 at the input data rate. The CLK1 signal can be differential or single-ended. If single-ended
either CLK1 or CLK1C can be used as input as long as the unused input is AC coupled to GND. Refer to
Figure 28 for the timing diagram. Unlike the DUAL SYNCHRONOUS CLOCK MODE, the t_{_align} parameter is not
critical because these clocks are not used as a synchronizing mechanism for the internal logic and the FIFO is
used as an elastic buffer for the data. Synchronizing in this mode is provided by separate control inputs.
CLK 2
D < t__align (only in dual synchronous clock mode)
CLK 1
(differential or single-ended)
DA [0 : 15 ]
DB [0 : 15 ]
t_s
t_h
Figure 28. DUAL (SYNCHRONOUS) CLOCK MODE Timing Diagram
EXTERNAL CLOCK MODE
In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through CLK2/C.
The CLKO_CLK1 pin is configured as an output in this mode and will toggle at a required frequency for the
configured interpolation rate and data mode. The CLKO_CLK1 clock can be used to drive the input data source
(such as digital upconverter) that sends the data to the DAC. Note that the CKO_CLK1 delay relative to the input
CLK2 rising edge (t_d(CLKO) in Figure 29) will increase with increasing loads.
CLK 2
CLKO _ CLK 1
(output )
t _d(CLKO)
DA [0 : 15 ]
DB [0 : 15 ]
ts _th
Figure 29. EXTERNAL CLOCK MODE Timing Diagram
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