DAC5689 Datasheet, PDF (3/48 Pages) Texas Instruments – 16-BIT 800 MSPS 2x-8x INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER (DAC)

DAC5689
www.ti.com .......................................................................................................................................................................................... SLLS989 – SEPTEMBER 2009
TERMINAL FUNCTIONS
NAME
AVDD
BIASJ
CLK2
CLK2C
TERMINAL
NO.
51, 54, 55,
59, 62
57
2
3
CLKO_CLK1
25
CLK1C
CLKVDD
DA[15..0]
26
1
7, 8, 11–24
DB[15..0]
DVDD
EXTIO
EXTLO
GND
IOUTA1
IOUTA2
IOUTB1
IOUTB2
IOVDD
NC
SYNC
RESETB
SCLK
SDENB
SDIO
SDO
40–43,
27–38
10, 39, 50,
63
56
58
4,
Thermal
Pad
52
53
61
60
9
64
5
49
47
48
46
45
I/O
DESCRIPTION
I Analog supply voltage. (3.3V)
O Full-scale output current bias. For 20mA full-scale output current, connect a 960 Ω resistor to GND.
I Positive DAC clock input. Accepts frequencies up to 800MHz.
I Complementary CLK2 input.
In Dual Clock Mode can be used to provide the lower frequency input clock. The lower frequency
I/O
clock can be differential or single-ended. If single-ended CLK1 can be used as the clock input.
CLK1C must be AC coupled to GND in this case. Optionally provides (CLKO) output for data bus
source. Internal pull-down.
In Dual Clock Mode can be used to provide the lower frequency input clock. The lower frequency
I/O
clock can be differential or single-ended. If differential, CLK1C is the complementary clock input. If
single-ended it can be used as the clock input. CLKO_CLK1 must be AC coupled to GND in this
case. Internal pull-down.
I
Internal clock buffer supply voltage. (1.8V)
It is recommended to isolate this supply from DVDD.
A-Channel Data Bits 0 through 15.
I
DA15 is most significant data bit (MSB) – pin 7
DA0 is least significant data bit (LSB) – pin 24
Internal pull-down. The order of bus can be reversed via CONFIG4 reva bit.
B-Channel Data Bits 0 through 15.
I
DB15 is most significant data bit (MSB) – pin 43
DB0 is least significant data bit (LSB) – pin 27
Internal pull-down. The order of bus can be reversed via CONFIG4 revb bit.
I
Digital supply voltage. (1.8V)
For best performance it is recommended to isolate pins 10 and 39 from all other 1.8V supplies.
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to
I/O AVDD). Used as internal reference output when EXTLO = GND, requires a 0.1µF decoupling
capacitor to GND when used as reference output
O Connect to GND for internal reference, or AVDD for external reference.
I
Pin 4 and the Thermal Pad located on the bottom of the QFN package is ground for AVDD, DVDD
and IOVDD supplies.
A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a
O
full scale current sink and the least positive voltage on the IOUTA1 pin. Similarly, a 0xFFFF data
input results in a 0 mA current sink and the most positive voltage on the IOUTA1 pin. In single DAC
mode, outputs appear on the IOUTA1/A2 pair only.
A-Channel DAC complementary current output. The IOUTA2 has the opposite behavior of the
O IOUTA1 described above. An input data value of 0x0000 results in a 0mA sink and the most positive
voltage on the IOUTA2 pin.
O B-Channel DAC current output. Refer to IOUTA1 description above.
O B-Channel DAC complementary current output. Refer to IOUTA2 description above.
I
3.3V supply voltage for all digital I/O. Note: This supply input should remain at 3.3V regardless of the
1.8V or 3.3V selectable digital input switching thresholds via CONFIG26 io_1p8_3p3.
I No connect. Leave open for proper operation.
I Optional SYNC input for internal clock dividers, FIFO, NCO and QMC blocks. Internal pull-down.
I Resets the chip when low. Internal pull-up.
I Serial interface clock. Internal pull-down.
I Active low serial data enable, always an input to the DAC5689. Internal pull-up.
I/O
Bi-directional serial data in 3-pin mode (default). In 4-pin interface mode (CONFIG5 sif4), the SDIO
pin is an input only. Internal pull-down.
O
Uni-directional serial interface data in 4-pin mode (CONFIG5 sif4). The SDO pin is 3-stated in 3-pin
interface mode (default). Internal pull-down.
Copyright © 2009, Texas Instruments Incorporated
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