BQ27541 Datasheet, PDF (31/38 Pages) Texas Instruments – Single Cell Li-Ion Battery Fuel Gauge for Battery Pack Integration

bq27541
www.ti.com ........................................................................................................................................................................................... SLUS861 – DECEMBER 2008
HDQ SINGLE-PIN SERIAL INTERFACE
The HDQ interface is an asynchronous return-to-one protocol where a processor sends the command code to
the bq27541. With HDQ, the least significant bit (LSB) of a data byte (command) or word (data) is transmitted
first. Note that the DATA signal on pin 12 is open-drain and requires an external pull-up resistor. The 8-bit
command code consists of two fields: the 7-bit HDQ command code (bits 0–6) and the 1-bit R/W field (MSB
bit 7). The R/W field directs the bq27541 either to
• Store the next 8 or 16 bits of data to a specified register or
• Output 8 or 16 bits of data from the specified register
The HDQ peripheral can transmit and receive data as either an HDQ master or slave.
The return-to-one data bit frame of HDQ consists of three distinct sections. The first section is used to start the
transmission by either the host or by the bq27541 taking the DATA pin to a logic-low state for a time t_(STRH,B).
The next section is for data transmission, where the data are valid for a time t_(DSU), after the negative edge used
to start communication. The data are held until a time t_(DV), allowing the host or bq27541 time to sample the data
bit. The final section is used to stop the transmission by returning the DATA pin to a logic-high state by at least a
time t_(SSU), after the negative edge used to start communication. The final logic-high state is held until the end of
t_(CYCH,B), allowing time to ensure the transmission was stopped correctly. The timing for data and break
communication are given in the HDQ characteristics section.
HDQ serial communication is normally initiated by the host processor sending a break command to the bq27541.
A break is detected when the DATA pin is driven to a logic-low state for a time t_(B) or greater. The DATA pin
should then be returned to its normal ready high logic state for a time t_(BR). The bq27541 is now ready to receive
information from the host processor.
The bq27541 is shipped in the I2C mode. TI provides tools to enable the HDQ peripheral.
Copyright © 2008, Texas Instruments Incorporated
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