BQ27510-G1 Datasheet, PDF (31/39 Pages) Texas Instruments – System-Side Impedance Track™ Fuel Gauge With Direct Battery Connection

bq27510-G1
www.ti.com ..................................................................................................................................................................................................... SLUS927 – APRIL 2009
COMMUNICATIONS
I²C INTERFACE
The bq27510 supports the standard I²C read, incremental read, quick read, one byte write, and incremental write
functions. The 7 bit device address (ADDR) is the most significant 7 bits of the hex address and is fixed as
1010101. The 8-bit device address will therefore be 0xAA or 0xAB for write or read, respectively.
Host generated
bq27510 generated
S ADDR[6:0] 0 A CMD[7:0] A DATA [7:0] A P S ADDR[6:0] 1 A DATA [7:0] N P
(a) 1-byte write
(b) quick read
S ADDR[6:0] 0 A CMD[7:0] A Sr ADDR[6:0] 1 A DATA[7:0] N P
(c) 1- byte read
S ADDR[6:0] 0 A CMD[7:0] A Sr ADDR[6:0] 1 A DATA[7:0] A . . . DATA[7:0] N P
(d) incremental read
S ADDR[6:0] 0 A CMD[7:0] A DATA [7:0] A DATA [7:0]
(e) incremental write
(S = Start, Sr = Repeated Start, A = Acknowledge, N = No Acknowledge, and P = Stop).
Figure 4. Supported I²C Formats
A ... A P
The “quick read” returns data at the address indicated by the address pointer. The address pointer, a register
internal to the I²C communication engine, will increment whenever data is acknowledged by the bq27510 or the
I²C master. “Quick writes” function in the same manner and are a convenient means of sending multiple bytes to
consecutive command locations (such as two-byte commands that require two bytes of data)
The following command sequences are not supported:
Attempt to write a read-only address (NACK after data sent by master):
S ADDR[6:0] 0 A CMD[7:0]
A DATA[7:0]
NP
Attempt to read an address above 0x6B (NACK command):
S
ADDR[6:0]
0 A CMD[7:0] N P
I²C TIME OUT
The I²C engine will release both SDA and SCL if the I2C bus is held low for about 2 seconds. If the bq27510 was
holding the lines, releasing them will free for the master to drive the lines. If an external condition is holding either
of the lines low, the I²C engine will enter the low power sleep mode.
I²C COMMAND WAITING TIME
To make sure the correct results of a command with the 400kHz I²C operation, a proper waiting time should be
added between issuing command and reading results. For subcommands, the following diagram shows the
waiting time required between issuing the control command the reading the status with the exception of
checksum command. A 100ms waiting time is required between the checksum command and reading result. For
read-write standard commands, a minimum of 2 seconds is required to get the result updated. For read-only
standard commands, there is no waiting time required, but the host should not issue all standard commands
more than two times per second. Otherwise, the gauge could result in a reset issue due to the expiration of the
watchdog timer.
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): bq27510-G1
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