MSP430X43X Datasheet, PDF (30/64 Pages) Texas Instruments – Mixed signal microcontroller

MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344B – JANUARY 2002 – REVISED OCTOBER 2002
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
output frequency
PARAMETER
f(Px.y)
(1 ≤ x ≤ 6, 0 ≤ y ≤ 7)
f(ACLK)
f(MCLK)
f(SMCLK)
P1.1/TA0/MCLK, P1.5/TACLK/
ACLK P1.4/TBCLK/SMCLK
t(Xdc)
Duty cycle of output frequency
TEST CONDITIONS
MIN
CL = 20 pF,
VCC = 2.2 V
DC
IL = ±1.5 mA
VCC = 3 V
DC
CL = 20 pF
P1.5/TACLK/ACLK,
CL = 20 pF
VCC = 2.2 V / 3 V
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(ACLK) = f(LFXT1) = f(XT1)
f(ACLK) = f(LFXT1) = f(LF)
f(ACLK) = f(LFXT1)
f(MCLK) = f(XT1)
f(MCLK) = f(DCOCLK)
f(SMCLK) = f(XT2)
f(SMCLK) = f(DCOCLK)
40%
30%
40%
50%–
15 ns
40%
50%–
15 ns
TYP
MAX
5
7.5
f(System)
50%
50%
50%
60%
70%
60%
50%+
15 ns
60%
50%+
15 ns
UNIT
MHz
MHz
inputs Px.x, TAx, TBx
PARAMETER
t(int)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
VCC
2.2 V/3 V
2.2 V
3V
MIN TYP MAX UNIT
1.5
cycle
62
ns
50
t(cap)
Timer_A, Timer_B capture
timing
TA0, TA1, TA2 (see Note 2)
TB0, TB1, TB2, TB3, TB4, TB5, TB6
(see Note 3)
2.2 V/3 V 1.5
2.2 V
62
3V
50
cycle
ns
f(TAext)
f(TBext)
Timer_A, Timer_B clock
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L)
2.2 V
3V
8
MHz
10
f(TAint) _{Timer_A, Timer_B clock}
f(BTAint) ^frequency
SMCLK or ACLK signal selected
2.2 V
3V
8
MHz
10
NOTES:
1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. The external capture signal triggers the capture event every time the minimum t(cap) cycle and time parameters are met. A capture
may be triggered with capture signals even shorter than t(cap). Both the cycle and timing specifications must be met to ensure a
correct capture of the 16-bit timer value and to ensure the flag is set.
3. Seven capture/compare registers in ’x44x and three capture/compare registers in ’x43x.
wake-up LPM3
PARAMETER
td(LPM3) Delay time
TEST CONDITIONS
f = 1 MHz
f = 2 MHz
f = 3 MHz
VCC = 2.2 V/3 V
MIN TYP MAX UNIT
6
6 µs
6
30
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