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MSP430X43X Datasheet, PDF (14/64 Pages) Texas Instruments – Mixed signal microcontroller
MSP430x43x, MSP430x44x
MIXED SIGNAL MICROCONTROLLER
SLAS344C – JANUARY 2002 – REVISED MARCH2003
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0FFFFh – 0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of 4xx Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh 15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
Timer_B7†
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
TBCCR0 CCIFG (see Note 2)
(Non)maskable
(Non)maskable
0FFFCh
14
(Non)maskable
Maskable
0FFFAh
13
Timer_B7†
TBCCR1 to TBCCR6 CCIFGs
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
ADC12
ADC12IFG (see Notes 1 and 2)
Maskable
0FFEEh
7
Timer_A3
TACCR0 CCIFG (see Note 2)
Maskable
0FFECh
6
Timer_A3
TACCR1 and TACCR2 CCIFGs,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
5
I/O Port P1 (Eight Flags)
USART1 Receive‡
USART1 Transmit‡
P1IFG.0 (see Notes 1 and 2)
To
P1IFG.7 (see Notes 1 and 2)
URXIFG1
UTXIFG1
Maskable
Maskable
Maskable
0FFE8h
4
0FFE6h
3
0FFE4h
2
I/O Port P2 (Eight Flags)
P2IFG.0 (see Notes 1 and 2)
To
P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
1
Basic Timer1
BTIFG
Maskable
0FFE0h 0, lowest
† ’43x uses Timer_B3 with TBCCR0, 1 and 2 CCIFG flags, and TBIFG. ’44x uses Timer_B7 with TBCCR0 CCIFG, TBCCR1 to TBCCR6 CCIFGs,
and TBIFG
‡ USART1 is implemented in ’44x only.
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable
it.
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