TLK2521 Datasheet, PDF (3/19 Pages) Texas Instruments – 1 to 2.5 Gbps TRANSCEIVER

functional block diagram
LOOPEN
TLK2521
1 to 2.5 Gbps TRANSCEIVER
SLLS574B − JULY 2003 − REVISED JANUARY 2004
TD(0−17)
18
Start/Stop
Encoder
20
Parallel to
Serial
Bit
Clock
GTX_CLK
TESTEN
ENABLE
Controls:
PLL,Bias,Rx,
Tx
Multiplying
Clock
Synthesizer
Bit
Clock
Interpolator and
Clock Recovery
MUX
DOUTTXP
DOUTTXN
PREEMPH
LOCKB
RX_CLK
Recovered
Clock
RD(0−17)
Start/Stop
18 _Decoder
20
Serial to
Parallel
MUX
DINRXP
DINRXN
transmit interface
The transmitter portion registers valid incoming 18-bit wide data (TXD[0:17]) on the rising edge of GTX_CLK.
The data is then framed with a start and a stop bit, serialized and transmitted sequentially over the differential
high-speed I/O channel. The clock multiplier multiplies the reference clock (GTX_CLK) by a factor of 10 times
creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register, which transmits data on
both the rising and falling edges of the bit clock providing a serial data rate that is 20 times the reference clock.
Data is transmitted LSB (D0) first.
transmit data bus
The transmit bus interface accepts 18-bit wide single-ended TTL parallel data at the TXD[0:17] pins. Data is
valid on the rising edge of GTX_CLK. The GTX_CLK is used as the word clock. The data and clock signals must
be properly aligned as shown in Figure 1. Detailed timing information can be found in the TTL input electrical
characteristics table.
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