TLK2521 Datasheet, PDF (10/19 Pages) Texas Instruments – 1 to 2.5 Gbps TRANSCEIVER

TLK2521
1 to 2.5 Gbps TRANSCEIVER
SLLS574B − JULY 2003 − REVISED JANUARY 2004
DISSIPATION RATING TABLE
PACKAGE
PAP64‡
TA ≤ 25°C
POWER RATING
3.22 W
DERATING FACTOR†
ABOVE TA = 25°C
32.15 mW/°C
TA = 70°C
POWER RATING
1.77 W
PAP64§
0.94 W
9.46 mW/°C
0.52 W
PAP64¶
0.68 W
6.78 mW/°C
0.37 W
† _{This is the inverse of the traditional junction-to-ambient thermal resistance (RθJA)}
‡ _{High K-board with solder}
§ _{High K-board without solder}
¶ _{Low K-board}
NOTE: For more information, see the TI application note PowerPAD Thermally Enhanced Package, TI (SLMA002).
electrical characteristics over recommended operating conditions
VDD
TA
PARAMETER
Supply voltage
Operating free-air temperature
ICC Supply current
PD Power dissipation
Shutdown current
PLL startup lock time
Data acquisition time
TEST CONDITION
VDD = 2.5 V, Freq = 1 Gb/sec, PRBS pattern
VDD = 2.5 V, Freq = 2.5 Gb/sec, PRBS pattern
VDD = 2.5 V, Freq = 1 Gb/sec, PRBS pattern
VDD = 2.5 V, Freq = 2.5 Gb/sec, PRBS pattern
VDD = 2.75 V, Freq = 2.5 Gb/sec, worst case pattern
ENABLE = 0, VDDA, VDD pins, VDD = max
VDD, VDDA = 2.3 V, EN ↑ to PLL acquire
MIN TYP MAX UNIT
2.3 2.5 2.7 V
−40
85 °C
71
mA
170
178
424
mW
730
130
µA
0.1 0.4 ms
1024
bits
reference clock (GTX_CLK) timing requirements over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
R_ω Frequency
Minimum data rate
Maximum data rate
Frequency tolerance
Duty cycle
Jitter#
Peak-to-peak
# _{See the Reference Lock Jitter Analysis For TLK2521 application note for more information.}
MIN
TYP−0.01%
TYP−0.01%
−100
40%
TYP
50
125
50%
MAX
TYP+0.01%
TYP+0.01%
100
60%
40
UNIT
MHz
MHz
ppm
ps
10
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