TLC2943 Datasheet, PDF (3/27 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
TERMINAL
NAME
NO.
GND
8, 31
12, 27
FIN–A_1,
4
FIN–B_1
5
FIN–A_2,
16
FIN–B_2
17
LOGIC_1 GND
7
LOGIC_2 GND
19
LOGIC_1 VDD
1
LOGIC_2 VDD
NC
13
9, 10,
11, 20,
28, 29,
30, 32
PFD_1 INHIBIT 33
PFD_2 INHIBIT 21
PFD_1 OUT
6
PFD_2 OUT
18
RBIAS_1
37
RBIAS_2
25
TEST_1
2
TEST_2
14
VCO_1 GND
35
VCO_2 GND
23
VCO_1 INHIBIT 34
VCO_2 INHIBIT 22
VCO_1 OUT
3
VCO_2 OUT
15
VCO_1 VDD
38
VCO_2 VDD
26
VCOIN_1
36
VCOIN_2
24
Terminal Functions
SLAS249 – NOVEMBER 1999
I/O
DESCRIPTION
Common GND for chip 1
Common GND for chip 2
Reference frequency signal input and comparison frequency signal input for PFD_1. fREF–IN_1 inputs
I to FIN-A_1, and comparison frequency input from external counter logic to FIN–B_1, for a lag-lead filter
use as LPF.
Reference frequency signal input and comparison frequency signal input for PFD_2. fREF–IN_2 inputs
I to FIN-A_2, and comparison frequency input from external counter logic to FIN-B_2, for a lag-lead filter use
as LPF.
Ground for the internal logic of chip 1
Ground for the internal logic of chip 2
Power supply for the internal logic of chip 1. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
Power supply for the internal logic of chip 2. This power supply should be separate from VCO VDD to
reduce cross-coupling between supplies.
No internal connection
I
PFD inhibit control for chip 1. When PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state,
see Table 2.
I
PFD inhibit control for chip 2. When PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state,
see Table 2.
O PFD output of chip 1. When the PFD_1 INHIBIT is high, PFD_1 OUT is in the high-impedance state.
O PFD output of chip 2. When the PFD_2 INHIBIT is high, PFD_2 OUT is in the high-impedance state.
I
Bias supply for VCO_1. An external resistor (RBIAS) between VCO_1 VDD and BIAS_1 supplies bias for
adjusting the oscillation frequency range of VCO_1.
I
Bias supply for VCO_2. An external resistor (RBIAS) between VCO_2 VDD and BIAS_2 supplies bias for
adjusting the oscillation frequency range of VCO_2.
Test terminal. TEST connects to LOGIC_1 GND for normal operation.
Test terminal. TEST connects to LOGIC_2 GND for normal operation.
GND for VCO_1
GND for VCO_2
I VCO inhibit control for chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low (see Table 1).
I VCO inhibit control for chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low (see Table 1).
O VCO output of chip 1. When VCO_1 INHIBIT is high, VCO_1 OUT is low.
O VCO output of chip 2. When VCO_2 INHIBIT is high, VCO_2 OUT is low.
Power supply for VCO_1. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
Power supply for VCO_2. This power supply should be separate from LOGIC VDD to reduce
cross-coupling between supplies.
VCO_1 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
I _{oscillation frequency.}
I
VCO_2 control voltage input. Nominally the external loop filter output connects to VCO IN to control VCO
oscillation frequency.
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