TLC2943 Datasheet, PDF (25/27 Pages) Texas Instruments – HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK

TLC2943
HIGH-PERFORMANCE DUAL PHASE-LOCKED BUILDING BLOCK
APPLICATION INFORMATION
SLAS249 – NOVEMBER 1999
PCB layout considerations
The TLC2943 contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2943 user:
D External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
D RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
D Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
D LOGIC V_DD and VCO V_DD should be separate PCB traces and connected to the best filtered supply point
available in the system to minimize supply cross-coupling.
D VCO V_DD to GND and LOGIC V_DD to GND should be decoupled with a 0.1-µF capacitor placed as close
as possible to the appropriate device terminals.
D The no-connection (NC) terminal on the package should be connected to GND.
The evaluation and operation schematic for the TLC2943 is shown in Figure 22.
REF IN
VDD
PLL1
1
LOGIC VDD (digital)
2
TEST
3 _{VCO OUT}
4 FIN – A
VCO
38
VCO VDD
37
BIAS
36
VCOIN
35
VCO GND
AVDD
R1†
0.22 µF
R3
C2
R2
C1
DGND
5 FIN – B
6 ^{PFD OUT}
Phase
Comparator
7
LOGIC GND (Digital)
VCOINHIBIT 34
PFD INHIBIT ₃₃
31
GND
AGND
Divide
By
N
DGND
PLL2
S1
S2
† _{RBIAS resistor}
R5 R6
DGND
DVDD
Figure 22. Evaluation and Operation Schematic
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
25