LM3485_15 Datasheet, PDF (3/24 Pages) Texas Instruments – Hysteretic PFET Buck Controller

LM3485
www.ti.com
SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013
Electrical Characteristics
Specifications in Standard type face are for T_J = 25°C, and in bold type face apply over the full Operating Temperature
Range (T_J = −40°C to +125°C). Unless otherwise specified, V_IN = 12V, V_ISNS = V_IN − 1V, and V_ADJ = V_IN − 1.1V. Datasheet
min/max specification limits are specified by design, test, or statistical analysis.
Symbol
Parameter
Test Conditions
Min ⁽¹⁾
Typ ⁽²⁾
Max ⁽¹⁾
Unit
I_Q
Quiescent Current at ground pin FB = 1.5V
(Not Switching)
250
400
µA
V_FB
Feedback Voltage
(3)
1.226
1.242
1.258
V
1.217
1.267
V_HYST
Comparator Hysteresis
V_CL ⁽⁴⁾
V_{CL_OFFSET}
I_{CL_ADJ}
T_CL
R_PGATE
I_PGATE
I_FB
T_{ONMIN_NOR}
T_{ONMIN_CL}
%V_FB/ΔV_IN
Current limit comparator trip voltage
Current limit comparator offset
Current limit ADJ current source
Current limit one shot off time
Driver resistance
Driver Output current
FB pin Bias Current⁽⁵⁾
Minimum on time in normal
operation
Minimum on time in current limit
Feedback Voltage Line Regulation
R_ADJ = 20kΩ
R_ADJ = 160kΩ
V_FB = 1.5V
V_FB = 1.5V
V_ADJ = 11.5V
V_ISNS = 11.0V
V_FB = 1.0V
Source
I_SOURCE = 100mA
Sink
I_Sink = 100mA
Source
V_IN = 7V,
P_GATE = 3.5V
Sink
V_IN = 7V,
P_GATE = 3.5V
V_FB = 1.0V
V_ISNS = V_ADJ+0.1V
C_load on OUT = 1000pF⁽⁶⁾
V_ISNS = V_ADJ+0.1V
V_FB = 1.0V
C_load on OUT = 1000pF⁽⁶⁾
4.5 ≤ V_IN ≤ 35V
10
15
mV
14
20
110
mV
880
−20
0
+20
mV
3.0
5.5
7.0
µA
6
9
14
µs
5.5
Ω
8.5
0.44
A
0.32
300
750
nA
100
ns
175
ns
0.010
%/V
(1) All limits are specified at room temperature (standard type face) and at temperature extremes (bold type face). All room temperature
limits are 100% tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) The V_FB is the trip voltage at the FB pin when PGATE switches from high to low.
(4) V_CL = I_{CL_ADJ} * R_ADJ
(5) Bias current flows out from the FB pin.
(6) A 1000pF capacitor is connected between V_IN and PGATE.
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