LM3485_15 Datasheet, PDF (15/24 Pages) Texas Instruments – Hysteretic PFET Buck Controller

LM3485
www.ti.com
SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013
The R_DSON is used in determining the current limit resistor value, R_ADJ. Note that the R_DSON has a positive
temperature coefficient. At 100°C, the R_DSON may be as much as 150% higher than the 25°C value. This
increase in R_DSON must be considered it when determining R_ADJ in wide temperature range applications. If the
current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.
Keeping the gate capacitance below 2000pF is recommended to keep switching losses and transition times low.
This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation
within the controller.
As gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases
operating frequency can be increased.
PCB Layout
The PC board layout is very important in all switching regulator designs. Poor layout can cause switching noise
into the feedback signal and general EMI problems. For minimal inductance, the wires indicated by heavy lines
should be as wide and short as possible. Keep the ground pin of the input capacitor as close as possible to the
anode of the diode. This path carries a large AC current. The switching node, the node with the diode cathode,
inductor, and FET drain, should be kept short. This node is one of the main sources for radiated EMI since it is
an AC voltage at the switching frequency. It is always good practice to use a ground plane in the design,
particularly at high currents.
The two ground pins, PWR GND and GND, should be connected by as short a trace as possible; they can be
connected underneath the device. These pins are resistively connected internally by approximately 50Ω. The
ground pins should be tied to the ground plane, or to a large ground trace in close proximity to both the FB
divider and C_OUT grounds.
The gate pin of the external PFET should be located close to the PGATE pin. However, if a very small FET is
used, a resistor may be required between PGATE and the gate of the FET to reduce high frequency ringing.
Since this resistor will slow the PFET's rise time, the current limit blanking time should be taken into
consideration (see CURRENT LIMIT OPERATION).
The feedback voltage signal line can be sensitive to noise. Avoid inductive coupling to the inductor or the
switching node, by keeping the FB trace away from these areas.
Figure 7. Typical PCB Layout Schematic (3.3V output)
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