DRV8844_15 Datasheet, PDF (3/25 Pages) Texas Instruments – DRV8844 Quad ½-H-Bridge Driver IC

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6 Pin Configuration and Functions
DRV8844
SLVSBA2C – JULY 2012 – REVISED MAY 2015
CP1 1
CP2 2
VCP 3
VM 4
OUT1 5
VNEG 6
OUT2 7
OUT3 8
VNEG 9
OUT4 10
VM 11
NC 12
NC 13
VNEG 14
PWP Package
28-Pin HTSSOP
Top View
GND
(PPAD)
28 VNEG
27 IN1
26 EN1
25 IN2
24 EN2
23 IN3
22 EN3
21 IN4
20 EN4
19 LGND
18 nFAULT
17 nSLEEP
16 nRESET
15 V3P3OUT
PIN
NAME
NO.
POWER AND GROUND
CP1
1
CP2
2
LGND
19
V3P3OUT
15
VCP
3
VM
4, 11
VNEG
CONTROL
EN1
EN2
EN3
EN4
IN1
IN2
IN3
IN4
nRESET
6, 9, 14,
28, PPAD
26
24
22
20
27
25
23
21
16
nSLEEP
17
STATUS
nFAULT
18
I/O ⁽¹⁾
Pin Functions
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
P Charge pump flying capacitor
P Charge pump flying capacitor
Connect a 0.01-μF 100-V capacitor between CP1 and
CP2.
P Logic input reference ground
Connect to logic ground. This may be any voltage between
VNEG and VM - 8 V.
P 3.3-V regulator output
Bypass to VNEG with a 0.47-μF 6.3-V ceramic capacitor.
Can be used to supply VREF.
P High-side gate drive voltage
Connect a 0.1-μF 16-V ceramic capacitor to VM.
P Main power supply
Connect to motor supply (8 V - 60 V). Both pins must be
connected to same supply. Bypass to VNEG with a 10-µF
(minimum) capacitor.
P
Negative power supply (dual
supplies) or ground (single supply)
I Channel 1 enable
I Channel 2 enable
I Channel 3 enable
I Channel 4 enable
I Channel 1 input
I Channel 2 input
I Channel 3 input
I Channel 4 input
I Reset input
I Sleep mode input
Logic high enables OUT1. Internal pulldown.
Logic high enables OUT2. Internal pulldown.
Logic high enables OUT3. Internal pulldown.
Logic high enables OUT4. Internal pulldown.
Logic input controls state of OUT1. Internal pulldown.
Logic input controls state of OUT2. Internal pulldown.
Logic input controls state of OUT3. Internal pulldown.
Logic input controls state of OUT4. Internal pulldown.
Active-low reset input initializes internal logic and disables
the H-bridge outputs. Internal pulldown.
Logic high to enable device, logic low to enter low-power
sleep mode. Internal pulldown.
OD Fault
Logic low when in fault condition (overtemp, overcurrent,
UVLO). Open-drain output.
(1) I = input, O = output, OD = open-drain output, P = power
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