DRV8844_15 Datasheet, PDF (11/25 Pages) Texas Instruments – DRV8844 Quad ½-H-Bridge Driver IC

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DRV8844
SLVSBA2C – JULY 2012 – REVISED MAY 2015
The charge pump requires two external capacitors for operation. Refer to the block diagram and pin descriptions
for details on these capacitors (value, connection, and so forth).
The charge pump is shut down when nSLEEP is low.
VM
VM
10uF
0.01uF
100V
CP1
CP2
Charge
Pump
VCP
0.1uF
16V
To pre-drivers
Figure 7. Charge Pump
8.3.5 Protection Circuits
The DRV8844 is fully protected against undervoltage, overcurrent and overtemperature events.
8.3.5.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the OCP deglitch time, the channel experiencing the overcurrent will
be disabled and the nFAULT pin will be driven low. The driver will remain off until either RESET is asserted or
VM power is cycled.
Overcurrent conditions on both high and low side devices; i.e., a short to ground, supply, or across the motor
winding will all result in an overcurrent shutdown.
8.3.5.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge will be disabled and the nFAULT pin will be
driven low. Once the die temperature has fallen to a safe level operation will automatically resume.
8.3.5.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all outputs will
be disabled, internal logic will be reset, and the nFAULT pin will be driven low. Operation will resume when VM
rises above the UVLO threshold.
8.4 Device Functional Modes
8.4.1 nRESET and nSLEEP Operation
The nRESET pin, when driven active low, resets the internal logic. It also disables the H-bridge drivers. All inputs
are ignored while nRESET is active.
Driving nSLEEP low will put the device into a low power sleep state. In this state, the H-bridges are disabled, the
gate drive charge pump is stopped and all internal clocks are stopped. In this state all inputs are ignored until
nSLEEP returns inactive high. When returning from sleep mode, some time (approximately 1 ms) needs to pass
before the motor driver becomes fully operational. Note that nRESET and nSLEEP have internal pulldown
resistors of approximately 100 kΩ. These signals need to be driven to logic high for device operation.
The V3P3OUT LDO regulator remains operational in sleep mode.
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