DRV8833_15 Datasheet, PDF (3/28 Pages) Texas Instruments – DRV8833 Dual H-Bridge Motor Driver

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5 Pin Configuration and Functions
DRV8833
SLVSAR1E – JANUARY 2011 – REVISED JULY 2015
nSLEEP 1
AOUT1 2
AISEN 3
AOUT2 4
BOUT2 5
BISEN 6
BOUT1 7
nFAULT 8
PWP Package
16-Pin HTSSOP
Top View
GND
(PPAD )
16 AIN1
15 AIN2
14 VINT
13 GND
12 VM
11 VCP
10 BIN2
9 BIN1
RTY Package
16-Pin WQFN
Top View
AISEN 1
AOUT2 ²
BOUT2 ³
BISEN ⁴
GND
(PPAD)
12 _VINT
11 _GND
10 _VM
9 _VCP
nSLEEP 1
AOUT1 2
AISEN 3
AOUT2 4
BOUT2 5
BISEN 6
BOUT1 7
nFAULT 8
PW Package
16-Pin TSSOP
Top View
16 AIN1
15 AIN2
14 VINT
13 GND
12 VM
11 VCP
10 BIN2
9 BIN1
PIN
NAME
WQFN
POWER AND GROUND
GND
11
PPAD
VINT
12
HTSSOP,
TSSOP
13
14
I/O ⁽¹⁾
Pin Functions
DESCRIPTION
—
Device ground. HTSSOP package
has PowerPAD.
— Internal supply bypass
VM
10
12
— Device power supply
VCP
9
CONTROL
AIN1
14
AIN2
13
BIN1
7
BIN2
8
11
IO High-side gate drive voltage
16
I
Bridge A input 1
15
I
Bridge A input 2
9
I
Bridge B input 1
10
I
Bridge B input 2
nSLEEP
15
1
I
Sleep mode input
(1) I = Input, O = Output, OZ = Tri-state output, OD = Open-drain output, IO = Input/output
EXTERNAL COMPONENTS
OR CONNECTIONS
Both the GND pin and device PowerPAD
must be connected to ground.
Bypass to GND with 2.2-μF, 6.3-V
capacitor.
Connect to motor supply. A 10-µF
(minimum) ceramic bypass capacitor to
GND is recommended.
Connect a 0.01-μF, 16-V (minimum) X7R
ceramic capacitor to VM.
Logic input controls state of AOUT1.
Internal pulldown.
Logic input controls state of AOUT2.
Internal pulldown.
Logic input controls state of BOUT1.
Internal pulldown.
Logic input controls state of BOUT2.
Internal pulldown.
Logic high to enable device, logic low to
enter low-power sleep mode and reset all
internal logic. Internal pulldown.
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