DRV8833_15 Datasheet, PDF (15/28 Pages) Texas Instruments – DRV8833 Dual H-Bridge Motor Driver

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10 Layout
DRV8833
SLVSAR1E – JANUARY 2011 – REVISED JULY 2015
10.1 Layout Guidelines
The VM pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value
of 10-μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace or
ground plane connection to the device GND pin.
A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. TI recommends a value of 0.01-
μF rated for 16 V. Place this component as close to the pins as possible.
Bypass VINT to ground with a 2.2-μF ceramic capacitor rated 6.3 V. Place this bypass capacitor as close to the
pin as possible.
10.1.1 Heatsinking
The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multilayer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, refer to TI application report, PowerPAD™ Thermally Enhanced
Package (SLMA002) and TI application brief, PowerPAD™ Made Easy (SLMA004), available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
NOTE
The PW package option is not thermally enhanced and TI recommends adhering to the
power dissipation limits.
10.2 Layout Example
R_AISEN
R_BISEN
nSLEEP
AOUT1
AISEN
AOUT2
BOUT2
BISEN
BOUT1
nFAULT
AIN1
AIN2
VINT
GND
VM
VCP
BIN2
BIN1
2.2 µF
.01 µF
10 µF
Figure 10. Recommended Layout Example
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