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DAC8531 Datasheet, PDF (3/19 Pages) Texas Instruments – Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER
ELECTRICAL CHARACTERISTICS (Cont.)
VDD = +2.7V to +5.5V. –40°C to +105°C, unless otherwise specified.
PARAMETER
LOGIC INPUTS (2)
Input Current
VINL, Input LOW Voltage
VINL, Input LOW Voltage
VINH, Input HIGH Voltage
VINH, Input HIGH Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (normal mode)
VDD = +3.6V to +5.5V
VDD = +2.7V to +3.6V
IDD (all power-down modes)
VDD = +3.6V to +5.5V
VDD = +2.7V to +3.6V
POWER EFFICIENCY
IOUT/IDD
TEMPERATURE RANGE
Specified Performance
CONDITIONS
MIN
VDD = +5V
VDD = +3V
VDD = +5V
2.4
VDD = +3V
2.1
2.7
DAC Active and Excluding Load Current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
ILOAD = 2mA, VDD = +5V
–40
DAC8531E
TYP
250
240
0.2
0.05
89
MAX
±1
0.8
0.6
3
5.5
400
390
1
1
+105
UNITS
µA
V
V
V
V
pF
V
µA
µA
µA
µA
%
°C
PIN CONFIGURATIONS
Top View
MSOP-8, SON-8
VDD 1
VREF 2
VFB 3
VOUT 4
DAC8531
8 GND
7 DIN
6 SCLK
5 SYNC
PIN DESCRIPTION
PIN NAME DESCRIPTION
1
VDD
Power-Supply Input, +2.7V to +5.5V.
2
VREF
Reference Voltage Input
3
VFB
Feedback connection for the output amplifier.
4
VOUT
Analog output voltage from DAC. The output ampli-
fier has rail-to-rail operation.
5
SYNC
Level-triggered control input (active LOW). This is
the frame sychronization signal for the input data.
When SYNC goes LOW, it enables the input shift
register and data is transferred in on the falling
edges of the following clocks. The DAC is updated
following the 24th clock cycle unless SYNC is taken
HIGH before this edge, in which case the rising
edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC8531.
6
SCLK
Serial Clock Input. Data can be transferred at rates
up to 30MHz.
7
DIN
Serial Data Input. Data is clocked into the 24-bit
input shift register on the falling edge of the serial
clock input.
8
GND
Ground reference point for all circuitry on the part.
DAC8531
3
SBAS192B
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