CDC586 Datasheet, PDF (3/12 Pages) Texas Instruments – 3.3-V PHASE-LOCK-LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS

CDC586
3.3-V PHASE-LOCK-LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS336D – FEBRUARY 1993 – REVISED OCTOBER 1998
output configuration A
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2x outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate
at the same frequency as CLKIN.
Table 1. Output Configuration A
output configuration B
INPUTS
OUTPUTS
1/2x
1x
SEL1 SEL0 _{FREQUENCY FREQUENCY}
L
L
None
All
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H 1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B
INPUTS
OUTPUTS
SEL1
SEL0
1x
FREQUENCY
2x
FREQUENCY
L
L
All
None
L
H
1Yn
2Yn, 3Yn, 4Yn
H
L
1Yn, 2Yn
3Yn, 4Yn
H
H 1Yn, 2Yn, 3Yn
4Yn
NOTE: n = 1, 2, 3
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