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BQ24100_10 Datasheet, PDF (3/40 Pages) Texas Instruments – SYNCHRONOUS SWITCHMODE, LI-ION AND LI-POLYMER CHARGE-MANAGEMENT IC WITH INTEGRATED POWER FETs ( bqSWITCHER™)
www.ti.com
bq24100, bq24103, bq24103A
bq24104, bq24105, bq24108, bq24109
bq24113, bq24113A, bq24115
SLUS606O – JUNE 2004 – REVISED MARCH 2010
PACKAGE DISSIPATION RATINGS
PACKAGE
RHL (1)
qJA
46.87°C/W
qJC
2.5°C/W
TA < 40°C
POWER RATING
1.81 W
DERATING FACTOR
ABOVE TA = 40°C
0.021 W/°C
(1) This data is based on using the JEDEC High-K board, and the exposed die pad is connected to a copper pad on the board. This is
connected to the ground plane by a 2x3 via matrix.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, VCC and IN (Tie together)
Operating junction temperature range, TJ
MIN
4.35 (1)
–40
NOM
MAX
16 (2)
125
UNIT
V
°C
(1) The IC continues to operate below Vmin, to 3.5 V, but the specifications are not tested and not specified.
(2) The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the IN or OUT pins. A tight layout
minimizes switching noise.
ELECTRICAL CHARACTERISTICS
TJ = 0°C to 125°C and recommended supply voltage range (unless otherwise stated)
PARAMETER
TEST CONDITIONS
INPUT CURRENTS
I(VCC)
VCC supply current
I(SLP)
Battery discharge sleep current, (SNS,
BAT, OUT, FB pins)
VOLTAGE REGULATION
VCC > VCC(min), PWM switching
VCC > VCC(min), PWM NOT switching
VCC > VCC(min), CE = HIGH
0°C ≤ TJ ≤ 65°C, VI(BAT) = 4.2 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
0°C ≤ TJ ≤ 65°C, VI(BAT) = 8.4 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
0°C ≤ TJ ≤ 65°C, VI(BAT) = 12.6 V,
VCC < V(SLP) or VCC > V(SLP) but not in charge
VOREG
Output voltage, bq24103/03A/04/13/13A
Output voltage, bq24100/08/09
CELLS = Low, in voltage regulation
CELLS = High, in voltage regulation
Operating in voltage regulation
VIBAT
Feedback regulation REF for bq24105/15
only (W/FB)
IIBAT = 25 nA typical into pin
Voltage regulation accuracy
TA = 25°C
CURRENT REGULATION - FAST CHARGE
IOCHARGE Output current range of converter
VLOWV ≤ VI(BAT) < VOREG,
V(VCC) - VI(BAT) > V(DO-MAX)
100 mV ≤ VIREG≤ 200 mV,
MIN
–0.5%
–1%
150
TYP
10
4.2
8.4
4.2
2.1
MAX UNIT
mA
5
315
mA
3.5
5.5
mA
7.7
V
V
0.5%
1%
2000
mA
VIREG
+
1V
RSET1
1000,
VIREG
Voltage regulated across R(SNS) Accuracy
Programmed Where
5 kΩ ≤ RSET1 ≤ 10 kΩ, Select RSET1 to
program VIREG,
VIREG(measured) = IOCHARGE + RSNS
(–10% to 10% excludes errors due to RSET1
and R(SNS) tolerances)
V(ISET1)
Output current set voltage
V(LOWV) ≤ VI(BAT) ≤ VO(REG),
V(VCC) ≤ VI(BAT) × V(DO-MAX)
K(ISET1)
Output current set factor
VLOWV ≤ VI(BAT) < VO(REG) ,
V(VCC) ≤ VI(BAT) + V(DO-MAX)
PRECHARGE AND SHORT-CIRCUIT CURRENT REGULATION
VLOWV
Precharge to fast-charge transition voltage
threshold, BAT,
bq24100/03/03A/04/05/08/09 ICs only
t
Deglitch time for precharge to fast charge Rising voltage;
transition,
tRISE, tFALL = 100 ns, 2-mV overdrive
–10%
1
1000
68
71.4
20
30
10%
V
V/A
75 %VO(REG)
40
ms
Copyright © 2004–2010, Texas Instruments Incorporated
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