BQ24100_10 Datasheet, PDF (29/40 Pages) Texas Instruments – SYNCHRONOUS SWITCHMODE, LI-ION AND LI-POLYMER CHARGE-MANAGEMENT IC WITH INTEGRATED POWER FETs ( bqSWITCHER™)

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bq24100, bq24103, bq24103A
bq24104, bq24105, bq24108, bq24109
bq24113, bq24113A, bq24115
SLUS606O – JUNE 2004 – REVISED MARCH 2010
PCB LAYOUT CONSIDERATION
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed
as close as possible to the bqSWITCHER. The output inductor should be placed directly above the IC and the
output capacitor connected between the inductor and PGND of the IC. The intent is to minimize the current
path loop area from the OUT pin through the LC filter and back to the GND pin. The sense resistor should be
adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the
R_(SNS) back to the IC, close to each other (minimize loop area) or on top of each other on adjacent layers (do
not route the sense leads through a high-current path). Use an optional capacitor downstream from the sense
resistor if long (inductive) battery leads are used.
• Place all small-signal components (C_TTC, RSET1/2 and TS) close to their respective IC pin (do not place
components such that routing interrupts power stage currents). All small control signals should be routed
away from the high current paths.
• The PCB should have a ground plane (return) connected directly to the return of all components through vias
(3 vias per capacitor for power-stage capacitors, 3 vias for the IC PGND, 1 via per capacitor for small-signal
components). A star ground design approach is typically used to keep circuit block currents isolated
(high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single
ground plane for this design gives good results. With this small layout and a single ground plane, there is not
a ground-bounce issue, and having the components segregated minimizes coupling between signals.
• The high-current charge paths into IN and from the OUT pins must be sized appropriately for the maximum
charge current in order to avoid voltage drops in these traces. The PGND pins should be connected to the
ground plane to return current through the internal low-side FET. The thermal vias in the IC PowerPAD™
provide the return-path connection.
• The bqSWITCHER is packaged in a thermally enhanced MLP package. The package includes a thermal pad
to provide an effective thermal contact between the IC and the PCB. Full PCB design guidelines for this
package are provided in the application report entitled: QFN/SON PCB Attachment (SLUA271). Six 10-13 mil
vias are a minimum number of recommended vias, placed in the IC's power pad, connecting it to a ground
thermal plane on the opposite side of the PWB. This plane must be at the same potential as V_SS and PGND
of this IC.
• See user guide SLUU200 for an example of good layout.
WAVEFORMS: All waveforms are taken at Lout (IC Out pin). V_IN = 7.6 V and the battery was set to 2.6 V, 3.5 V,
and 4.2 V for the three waveforms. When the top switch of the converter is on, the waveform is at ~7.5 V, and
when off, the waveform is near ground. Note that the ringing on the switching edges is small. This is due to a
tight layout (minimized loop areas), a shielded inductor (closed core), and using a low-inductive scope ground
lead (i.e., short with minimum loop) .
Copyright © 2004–2010, Texas Instruments Incorporated
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Product Folder Link(s): bq24100 bq24103 bq24103A bq24104 bq24105 bq24108 bq24109 bq24113 bq24113A
bq24115