BQ24030 Datasheet, PDF (3/20 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINYI)

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RECOMMENDED OPERATING CONDITIONS
V_CC Supply voltage (from AC input) ⁽¹⁾⁽²⁾
V_CC Supply voltage (from USB input) ⁽¹⁾
I_AC
Input current, AC
I_USB Input current, USB
T_J
Operating junction temperature range
(1) V_CC is defined as the greater of AC or USBinput.
(2) Verify that powerdissipation and junction temperatures are within limits at maximum V_CC .
bq24030, bq24032, bq24035
SLUS618 – AUGUST 2004
MIN MAX UNIT
4.35 16.00
V
4.35 6.5
2
A
0.5
-40 125 °C
DISSIPATION RATINGS
PACKAGE
20-pin RHL⁽¹⁾
T_A≤ 40°C
POWER RATING
1.81 W
DERATING FACTOR
T_A > 40°C
21 mW/°C
θ_JA
46.87 °C/W
(1) This data is based onusing the JEDEC High-K board and the exposed die pad is connected to a Cu padon the board. This is connected
to the ground plane by a 2×3 viamatrix.
ELECTRICAL CHARACTERISTICS
over junction temperature range (0°C ≤ T_J≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT CURRENT
I_CC(SPLY)
I_CC(SLP)
Active supply current, VCC
Sleep current (current into BAT
pin)
V_VCC > V_VCC(min)
V_(AC) < V_(UVLO), V_(USB) < V_(UVLO),
2.6 V ≤ V_I(BAT)≤ V_O(BAT-REG),
Excludes load on OUT pin
1
2 mA
2
5
I_CC(AS-STDBY) AC standby current
I_CC(USB-
STDBY)
USB standby current
I_{CC(BAT-STDBY)} BAT standby current
I_IB(BAT)
Charge done current, BAT
V_I(AC)≤ 6V, Total current into AC pin with
chip disabled, Excludes all loads, ⁽¹⁾
CE=LOW, after t_(CE-HOLDOFF) delay
Total current into USB pin with chip dis-
abled,
Excludes all loads, ⁽¹⁾CE=LOW,
after t_(CE-HOLDOFF) delay
Total current into BAT pin with AC and/or
USB present and chip disabled,
Excludes all loads,
CE=LOW, after t_(CE-HOLDOFF) delay⁽¹⁾
Charge DONE, AC or USB supplying the
load
200
200 µA
45
60
1
5
LDO OUTPUT
V_O(LDO)
Output regulation voltage
Regulation accuracy
Active only if AC or USB is present,
V_I(OUT)≥ V_O(LDO) + (I_O(LDO)× R_DS(on))
3.3
V
(2)_-5%
5%
I_O(LDO)
Output current
R_DS(on)
On resistance
C_(OUT)
Output capacitance
OUT TERMINAL AND DPPM MODE
OUT to LDO
20 mA
50 Ω
(3)_{1 µF}
V_O(OUT-REG)
V_(DPPM-SET)
I_(DPPM-SET)
Output regulation volt-
age
DPPM set point⁽⁴⁾
DPPM current source
bq24030 V_I(AC)≥ 6 V+V_DO
bq24032 V_I(AC)≥ 4.4 V+V_DO
AC or USB present
6.0
6.3
4.4
4.5 V
2.6
3.7
95
100
105 µA
(1) This includes thequiescent current for the integrated LDO.
(2) In standby mode (CElow) the accuracy is ±10%.
(3) LDO output capacitornot required but one with a value of 0.1-µF is recommended.
(4) V_(DPPM-SET) is scaled up by the scale factor forcontrolling the output voltage V_(DPPM-REG).
3