BQ24030 Datasheet, PDF (17/20 Pages) Texas Instruments – SINGLE-CHIP CHARGE AND SYSTEM POWER-PATH MANAGEMENT IC (bqTINYI)

bq24030, bq24032, bq24035
www.ti.com
APPLICATION INFORMATION
SLUS618 – AUGUST 2004
Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A
0.1-µF ceramic, placed in close proximity to AC and USB to VSS pins, works well. In some applications
depending on the power supply characteristics and cable length it may be necessary to add an additional 10-µF
ceramic to each input.
The bqTINY-III only requires a small output capacitor for loop stability. A 0.1-µF ceramic capacitor placed
between the OUT and VSS pin is typically sufficient.
The integrated LDO requires a maximum of 1-µF ceramic capacitor on its output. The output does not require a
capacitor for a steady state load but a 0.1-µF minimum capacitance is recommended.
It is recommended to install a minimum of 33-µF between the BAT pin and VSS (in parallel with the battery). This
ensures proper hot plug power-up with a no load condition (no system load or battery attached).
Thermal Considerations
The bqTINY-III is packaged in a thermally enhanced MLP package. The package includes a thermal pad to
provide an effective thermal contact between the device and the printed circuit board (PCB). Full PCB design
guidelines for this package are provided in the application note entitled: QFN/SON PCB Attachment (SLUA271).
The power pad should be tied to the VSS plane. The most common measure of package thermal performance is
thermal impedance (θ_JA) measured (or modeled) from the chip junction to the air surrounding the package
surface (ambient).
The mathematical expression for θ_JA is:
q_JA
+
T_J
*
P
T_A
(9)
where
• T_J = chip junction temperature
• T_A = ambient temperature
• P = device power dissipation
Factors that can greatly influence the measurement and calculation of θ_JA include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal
PowerFET. It can be calculated from Equation 10:
P + ^ƪǒV_IN * V_OUT^{Ǔ ǒ}I_OUT ) I_BAT^Ǔƫ ) ^ƪǒV_OUT * V_BAT^{Ǔ ǒ}I_BAT^Ǔƫ
(10)
Due to the charge profile of Li-xx batteries the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. Please see Figure 2. Typically the Li-Ion battery’s
voltage quickly (< 2 V minimum) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and
battery above 3 V). Therefore it is customary to perform the steady state thermal design using 3.5 V as the
minimum battery voltage since the system board and charging device doesn't have time to reach a maximum
temperature due to the thermal mass of the assembly during the early stages of fast charge. This theory is easily
verified by performing a charge cycle on a discharged battery while monitoring the battery voltage and charger’s
power pad temperature.
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