TMS320DM6437_08 Datasheet, PDF (292/305 Pages) Texas Instruments – Digital Media Processor

TMS320DM6437
Digital Media Processor
SPRS345D – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
Table 6-109. Timing Requirements for Receive Data for the VLYNQ Module⁽¹⁾ (see Figure 6-54)
-7/-6/-5/-4
NO.
-L/-Q6/-Q5/-Q4
UNIT
MIN
MAX
3
t_{su(RXDV-VCLKH)}
Setup time, VLYNQ_RXD[3:0] valid before ^{RTM disabled, RTM sample = 3}
VLYNQ_CLK high
RTM enabled
1.75
(1)
ns
ns
4
t_{h(VCLKH-RXDV)}
Hold time, VLYNQ_RXD[3:0] valid after
VLYNQ_CLK high
RTM disabled, RTM sample = 3
RTM enabled
3
(1)
ns
ns
(1) The VLYNQ receive timing manager (RTM) is a serial receive logic designed to eliminate setup and hold violations that could occur in
traditional input signals. RTM logic automatically selects the setup and hold timing from one of eight data flops (see Table 6-110). When
RTM logic is disabled, the setup and hold timing from the default data flop (3) is used.
Table 6-110. RTM RX Data Flop Hold/Setup Timing
Constraints (Typical Values)
RX Data Flop
0
1
2
3
4
5
6
7
HOLD (Y)
1.3
1.4
1.5
1.6
1.8
2.0
2.2
2.4
SETUP (X)
0.9
0.7
-0.4
-0.6
-0.8
-1.0
-1.1
-1.2
1
VLYNQ_CLK
2
VLYNQ_TXD[3:0]
VLYNQ_RXD[3:0]
Data
3
4
Data
Figure 6-54. VLYNQ Transmit/Receive Timing
292 Peripheral Information and Electrical Specifications
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