TIR2000 Datasheet, PDF (29/63 Pages) Texas Instruments – High-Speed Serial Infrared Controller With 64-Byte FIFO

2.1.7 DMA Operation
The DMA mode of data transfer is used to achieve faster data transfer when the device is operating in the
FIR or in the MIR modes. In a multi-application environment, where multiple applications are running at the
same time, the DMA mode should be used to keep up with the high rate of data transfer without having
underrun during data transmission or overrun during data receive. Frames can be transmitted and received
back-to-back. The device must be programmed for data transmission and data receive. The DCSR register
is programmed to select and enable the DMA channel for data transmit and data receive.
2.1.7.1 DMA Data-Transmit Mode
Packets of various sizes can be transmitted. Packets, smaller than 2k bytes, can be properly terminated
through the TC signal from the DMA controller or through the (TXFLH, TXFLL) registers value. Packets,
larger than 2k bytes, can be automatically fragmented into equal-sized smaller frames (decided by the
TXFLH and TXFLL registers value) and properly transmitted. The last portion of the packet, which may be
smaller than the (TXFLH, TXFLL) register value, is terminated by the TC signal. The DMA controller asserts
the TC signal when it sends the last byte of that packet. When the DMA asserts the TC signal, an interrupt
IIR[6] bit is generated to inform the CPU that the DMA data transmission is complete.
The DMA controller uses the Demand Transfer mode to transfer data from memory to the TXFIFO. The
peripheral device asserts the DRQ signal when the number of bytes in the TXFIFO falls below the set
threshold level and de-asserts the DRQ when the TXFIFO becomes almost full.
2.1.7.2 DMA Data-Receive Mode
The DMA controller controls the data reception of back-to-back frames. The back-to-back frames are
transferred to memory and the status of each received frame is stored in the Status FIFO which can hold
up to 8 entries. Each entry in the Status FIFO corresponds to one received frame. Each entry stores the
length of each received frame and the error-status of that frame. The CPU reads the Status FIFO entries
to locate the frame boundaries and status of individual frames inside memory.
The Status FIFO has 4 interrupt levels, which are 1, 4, 7, and 8. In a data receive transaction, the receiver
peripheral expects to receive 1 to 7 frames. When the number of received frames becomes equal or greater
than the set threshold value in the Status FIFO, the peripheral device generates an interrupt IIR[4] bit. After
the CPU receives the Status FIFO interrupt (IIR[4] bit), it reads the Status FIFO Register High (SFREGH)
and then the Status FIFO Register Low (SFREGL) to determine the length of the frame. The SFLSR register
is then read to determine the error-status of that frame. The CPU checks the content of the SFLSR[4] bit
which is set to a 1 when the Status FIFO becomes empty. If this bit is found to be a 1, the CPU should stop
reading the SFREFH, SFREGL, and SFLSR registers.
The time-out interrupt is set at 1 ms. This is useful when the number of frames in a data receive transaction
is less than the set Status FIFO threshold level. A time-out interrupt (IIR[2] bit) will be generated when the
inter-frame gap between back-to-back frames is 1 ms. When the CPU receives a Status FIFO time-out
interrupt, it should read the LSR register (LSR[1] bit) to find out the empty status of the Status FIFO. If the
Status FIFO is empty, the CPU disregards the interrupt. If the Status FIFO is not empty, the CPU reacts the
same as it does after receiving a Status FIFO threshold interrupt.
The DMA controller uses the demand transfer mode to transfer data from the RXFIFO to memory. The
peripheral device asserts the DRQ signal when the number of bytes in the RXFIFO is equal to or greater
than the set threshold level or when the end of a receive frame is detected by the RX state machine. The
DRQ is de-asserted when the RXFIFO becomes empty. An overrun in the RXFIFO in the DMA mode is
handled differently than in the programmed I/O mode. When an overrun occurs in the RXFIFO, during any
frame, data reception is terminated and the RX state machine waits for the next frame. It continues to receive
the further frames. The overrun error (OE bit) is set to a 1 in the SFLSR register for the frame in which a
RXFIFO overrun has occurred.
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