TIR2000 Datasheet, PDF (10/63 Pages) Texas Instruments – High-Speed Serial Infrared Controller With 64-Byte FIFO

1.5 Terminal Functions
TERMINALS
I/O
NAME
NO.
DESCRIPTION
A0 – A3
36–39 I Address bus. The CPU uses A0 -A3 and the CS signal to select the internal register
of the TIR2000. A0 -A3 are decoded to select a particular register.
CS
CTS
D0–D7
DACK0,
DACK1,
DACK3
DCD
30
I Chip select. The CPU uses CS to select the TIR2000 for read/write transactions.
54
I Clear to send. CTS is a modem-status signal. Its condition can be checked by reading
bit 4 (CTS) of the modem-status register (MSR). Bit 0 (∆CTS) of the MSR indicates
that CTS has changed states since the last read from the MSR. When modem-status
interrupt is enabled, CTS changes states, and the auto-CTS mode is not enabled, an
interrupt is generated. CTS is also used in the auto-CTS mode to control the
transmitter.
1–4, I/O Data bus. These bidirectional data lines are connected to the CPU for data transfer
6–9
between the TIR2000 and the CPU. D0 is the LSB and D7 is the MSB.
27–29 I DMA acknowledge. DACK0, DACK1, and DACK3 are DMA active low signals that
are the corresponding acknowledge signals, for the DMA request signals which are
DRQ0, DRQ1 and DRQ3.
56
I Data carrier detect. DCD is a modem-status signal. Its condition can be checked by
reading bit 7 (DCD) of the MSR. Bit 3 (∆DCD) of the MSR indicates that DCD has
changed states since the last read from the MSR. When the modem-status interrupt
is enabled and DCD changes state, an interrupt is generated.
DRQ0, DRQ1,
DRQ3
23–25
O DMA requests. DRQ0, DRQ1 and DRQ3 are used for DMA requests that are active
high and are used to signal the DMA controller that data transfer between the
TIR2000 and memory is required. When the DMA is enabled, one of the three
channels configurable through the DMA channel select register (DCSR) can be
selected.
DSR
55
I Data set ready. DSR is a modem-status signal. Its condition can be checked by
reading bit 5 (DSR) of the MSR. Bit 1 (∆DSR) of the MSR indicates the DSR has
changed states since the last read from the MSR. When the modem-status interrupt
is enabled and the DSR changes states, an interrupt is generated.
DTR
61 O Data terminal ready. When low, DTR informs a modem or data set that the UART is
ready to establish communication. DTR is placed in the active state by setting the
DTR bit of the modem-control register to one. DTR is placed in the inactive condition
as a result of a master reset, during loop mode operation, or clearing of the DTR bit.
GND
5, 10,
26, 34,
50
Ground (0 V). GND terminals must be tied to ground for proper operation.
GPIO0–GPIO3, 40–43, I/O General purpose I/O terminals. GPIO0–GPIO7 terminals are programmable
GPIO4–GPIO7 45–48
general-purpose input/output terminals.
IRQ3–IRQ7,
IRQ9–IRQ12,
IRQ14, IRQ15
11–16, O Interrupt signals. These active-high interrupts are activated based on the IRQ
18–22
configuration register.
IRRVH
64
I Infrared receive. IRRVH is an input connected to the IR transceiver module that
receives data in the high-speed modes (1.15 Mbps and 4 Mbps mode).
1–4