SN74SSTU32866 Datasheet, PDF (29/37 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTU32866
25ĆBIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSĆPARITY TEST
SCES564 − APRIL 2004
timing diagram for the second SN74SSTU32866 (1:2 Register-B configuration) device used in pair;
C0 = 1, C1 = 1 (RESET switches from L to H)
RESET
DCCSRS^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
CCLLKK^{ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
tact
ÎÎÎÎÎÎÎÎÎÎÎÎ _{D1−D14â€} 
Q1−Q14
PAR_IN†^{‡ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ}
PPO
(not used)
n
n+1
n+2
n+3
n+4
tsu
th
tpdm, tpdmss
CLK to Q
tsu
th
tpd
CLK to PPO
tPHL
CLK to QERR
tPHL, tPLH
CLK to QERR
QERR^§
Data to QERR Latency
ÎÎÎÎÎ _{H, L, or X}
H or L
ÎÎÎÎÎÎÎÎÎÎ _{† After RESET is switched from low to high, all data and PAR_IN input signals must be set and held low for a minimum time of tact max,}
to avoid false error.
‡ _{PAR_IN is driven from PPO of the first SN74SSTU32866 device.}
§ _{If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on the}
n + 3 clock pulse.
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