SN74SSTU32866 Datasheet, PDF (23/37 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTU32866
25ĆBIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSĆPARITY TEST
SCES564 − APRIL 2004
timing diagram for SN74SSTU32866 used as a single device; C0 = 0, C1 = 0
(RESET = H)
RESET
DCCCCSLLRKKS_{ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ}
n
n+1
n+2
ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ _D1−D25
tsu
tpdm, tpdmss
th
CLK to Q
Q1−Q25^{ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ}
PAR_IN^{ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇ tsu}
th
QEPRPRO^{†ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇDÇÇÇÇÇÇata ÇÇÇÇÇÇto CPLPÇÇÇÇÇÇKOtLoaPtetPpnOdcy}
Data to QERR Latency
n+3
n+4
tPHL or tPLH
CLK to QERR
ÉÉÉÉ_{Unknown input}
ÉÉÉÉ^event
ÇÇÇÇ _{Output signal is dependent on}
ÇÇÇÇ ^{the prior unknown input event}
H or L
† _{If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n + 2 clock pulse, and it will be valid on n + 3}
clock pulse. If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven
low.
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