SN74SSTU32866 Datasheet, PDF (11/37 Pages) Texas Instruments – 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

SN74SSTU32866
25ĆBIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSĆPARITY TEST
SCES564 − APRIL 2004
parity logic diagram for 1:2 register-B configuration (positive logic); C0 = 1, C1 = 1
RESET ^G2
CLK ^H1
CLK ^J1
D1−D6,
D8-D13
11
VREF ^{A3, T3}
LPS0
(internal node)
D ^CE
CLK Q
R
11
D1−D6,
D8−D13
D1−D6,
D8−D13
11
11 _{Q1A−Q6A,}
Q8A−Q13A
11 _{Q1B−Q6B,}
Q8B−Q13B
G5
C1
G1
PAR_IN
Parity
Generator
0
DQ
1
CLK
R
DQ
CLK
R
CE
1
D _Q0
CLK
R
A2
PPO
D2
QERR
G6
C0
CLK
2−Bit
Counter
R
LPS1
(internal node)
0
D
Q
1
CLK
R
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