BQ24193_15 Datasheet, PDF (29/49 Pages) Texas Instruments – bq24193 I2C Controlled 4.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

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8.5.1.3 Charge Current Control Register REG02 (reset = 01100000, or 60)
SLUSBG7 – DECEMBER 2014
Figure 25. REG02 Charge Current Control Register Format
7
6
5
4
ICHG[5]
ICHG[4]
ICHG[3]
ICHG[2]
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
ICHG[1]
R/W
2
ICHG[0]
R/W
1
Reserved
R/W
0
FORCE_20PCT
R/W
Table 9. REG02 Charge Current Control Register Description
BIT FIELD
Fast Charge Current Limit
Bit 7 ICHG[5]
Bit 6 ICHG[4]
Bit 5 ICHG[3]
Bit 4 ICHG[2]
Bit 3 ICHG[1]
Bit 2 ICHG[0]
Bit 1 Reserved
Bit 0 FORCE_20PCT
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RESET
0
1
1
0
0
0
0
0
DESCRIPTION
NOTE
2048 mA
1024 mA
512 mA
256 mA
128 mA
64 mA
0 - Reserved
0 – ICHG as REG02[7:2] programmed
1 – ICHG as 20% of REG02[7:2]
programmed
Offset: 512 mA
Range: 512 to 4544 mA
Default: 2048 mA (011000)
Reserved. Must write "0"
Default: ICHG as REG02[7:2] programmed
(0)
8.5.1.4 Pre-Charge/Termination Current Control Register REG03 (reset = 00010001, or 11)
Figure 26. REG03 Pre-Charge/Termination Current Control Register Format
7
6
5
4
IPRECHG[3] IPRECHG[2] IPRECHG[1] IPRECHG[0]
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
3
ITERM[3]
R/W
2
ITERM[2]
R/W
1
ITERM[1]
R/W
0
ITERM[0]
R/W
Table 10. REG03 Pre-Charge/Termination Current Control Register Description
BIT FIELD
Pre-Charge Current Limit
Bit 7 IPRECHG[3]
Bit 6 IPRECHG[2]
Bit 5 IPRECHG[1]
Bit 4 IPRECHG[0]
Termination Current Limit
Bit 3 ITERM[3]
Bit 2 ITERM[2]
Bit 1 ITERM[1]
Bit 0 ITERM[0]
TYPE RESET
R/W 0
R/W 0
R/W 0
R/W 1
R/W 0
R/W 0
R/W 0
R/W 1
DESCRIPTION
1024 mA
512 mA
256 mA
128 mA
1024 mA
512 mA
256 mA
128 mA
NOTE
Offset: 128 mA,
Range: 128 mA to 2048 mA
Default: 256 mA (0001)
Offset: 128 mA
Range: 128 mA to 2048 mA
Default: 256 mA (0001)
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