OPA3690ID Datasheet, PDF (28/39 Pages) Texas Instruments – Triple, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable

OPA3690
SBOS237G – MARCH 2002 – REVISED MARCH 2010
www.ti.com
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a
high-frequency amplifier like the OPA3690 requires
careful attention to board layout parasitics and
external component types. Recommendations that
will optimize performance include:
a. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
b. Minimize the distance (< 0.25") from the
power-supply pins to high-frequency 0.1mF
decoupling capacitors. At the device pins, the
ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power-supply connections should
always be decoupled with these capacitors. An
optional supply decoupling capacitor (0.1mF)
across the two power supplies (for bipolar
operation) will improve 2nd-harmonic distortion
performance. Larger (2.2mF to 6.8mF) decoupling
capacitors, effective at lower frequencies, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PCB.
c. Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA3690. Resistors should
be a very low reactance type. Surface-mount
resistors work best and allow a tighter overall
layout. Metal film or carbon composition
axially-leaded resistors can also provide good
high-frequency performance. Again, keep their
leads and PCB traces as short as possible. Never
use wirewound type resistors in a high-frequency
application. Since the output pin and inverting
input pin are the most sensitive to parasitic
capacitance, always position the feedback and
series output resistor, if any, as close as possible
to the output pin. Other network components,
such as noninverting input termination resistors,
should also be placed close to the package.
Where double-side component mounting is
allowed, place the feedback resistor directly
under the package on the other side of the board
between the output and inverting input pins. Even
with a low parasitic capacitance shunting the
external resistors, excessively high resistor
values can create significant time constants that
can degrade performance. Good axial metal film
or surface-mount resistors have approximately
0.2pF in shunt with the resistor. For resistor
values > 1.5kΩ, this parasitic capacitance can
add a pole and/or zero below 500MHz that can
affect circuit operation. Keep resistor values as
low as possible consistent with load driving
considerations. The 402Ω feedback used in the
Electrical Characteristics is a good starting point
for design. Note that a 25Ω feedback resistor,
rather than a direct short, is suggested for the
unity-gain follower application. This effectively
isolates the inverting input capacitance from the
output pin that would otherwise cause an
additional peaking in the gain of +1 frequency
response.
d. Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50mils or 1,27mm to
100mils or 2,54mm) should be used, preferably
with ground and power planes opened up around
them. Estimate the total capacitive load and set
R_S from the plot of Recommended R_S vs
Capacitive Load (Figure 15 for ±5V and Figure 30
for +5V). Low parasitic capacitive loads (< 5pF)
may not need an R_S because the OPA3690 is
nominally compensated to operate with a 2pF
parasitic load. Higher parasitic capacitive loads
without an R_S are allowed as the signal gain
increases (increasing the unloaded phase
margin). If a long trace is required, and the 6dB
signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline
layout techniques). A 50Ω environment is
normally not necessary on board, and in fact, a
higher impedance environment will improve
distortion as shown in the distortion versus load
plots (Figure 7 for the ±5v and Figure 32 for the
+5V). With a characteristic board trace
impedance defined (based on board material and
trace dimensions), a matching series resistor into
the trace from the output of the OPA3690 is used
as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance will be the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the
trace impedance. The high output voltage and
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