OPA3690ID Datasheet, PDF (26/39 Pages) Texas Instruments – Triple, Wideband, Voltage-Feedback OPERATIONAL AMPLIFIER with Disable

OPA3690
SBOS237G – MARCH 2002 – REVISED MARCH 2010
DISABLE OPERATION
The OPA3690 provides an optional disable feature on
each channel that may be used either to reduce
system power or to implement a simple channel
multiplexing operation. If the DIS control pin is left
unconnected, the OPA3690 will operate normally. To
disable, the control pin must be asserted LOW.
Figure 52 shows a simplified internal circuit for the
disable control feature available on each channel.
+V_S
15kW
Q1
V_DIS
25kW
I_S
Control
110kW
-V_S
Figure 52. Simplified Disable Control Circuit
In normal operation, base current to Q1 is provided
through the 110kΩ resistor, while the emitter current
through the 15kΩ resistor sets up a voltage drop that
is inadequate to turn on the two diodes in Q1's
emitter. As V_DIS is pulled LOW, additional current is
pulled through the 15kΩ resistor, eventually turning
on those two diodes (≈75mA). At this point, any
further current pulled out of V_DIS goes through those
diodes holding the emitter-base voltage of Q1 at
approximately 0V. This shuts off the collector current
out of Q1, turning the amplifier off. The supply current
in the disable mode are only those required to
operate the circuit of Figure 52. Additional circuitry
ensures that turn-on time occurs faster than turn-off
time (make-before-break).
When disabled, the output and input nodes go to a
high-impedance state. If the OPA3690 is operating at
a gain of +1, this will show a very high impedance at
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the output and exceptional signal isolation. If
operating at a gain greater than +1, the total
feedback network resistance (R_F + R_G) will appear as
the impedance looking back into the output, but the
circuit will still show very high forward and reverse
isolation. If configured as an inverting amplifier, the
input and output will be connected through the
feedback network resistance (R_F + R_G) and the
isolation will be very poor as a result.
One key parameter in disable operation is the output
glitch when switching in and out of the disabled
mode. Figure 53 shows these glitches for the circuit
of Figure 36 with the input signal at 0V. The glitch
waveform at the output pin is plotted along with the
DIS pin voltage.
The transition edge rate (dV/dt) of the DIS control line
will influence this glitch. For the plot of Figure 53, the
edge rate was reduced until no further reduction in
glitch amplitude was observed. This approximately
1V/ns maximum slew rate may be achieved by
adding a simple RC filter into the DIS pin from a
higher speed logic line. If extremely fast transition
logic is used, a 1kΩ series resistor between the logic
gate and the DIS input pin provides adequate
bandlimiting using just the parasitic input capacitance
on the DIS pin while still ensuring adequate logic
level swing.
40
Output Voltage
20
(0V Input)
0
-20
-40
V_DIS
4.8V
0.2V
Time (20ns/div)
Figure 53. Disable/Enable Glitch
26
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