GC5330 Datasheet, PDF (28/49 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC5330
GC5337
SLWS226 B – DECEMBER 2010 – REVISED JANUARY 2011
CEB
Write Cycle
Read Cycle
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Addr
OEB
WEB
Data
Figure 14. MPU Interface Format
T0506-01
Serial Peripheral Interface (SPI)
The MPU and SPI interfaces can be only enabled one at a time. EMIFENA must be set to logic low to enable the
SPI interface. A three- or four-wire SPI interface is supported in the GC533x. It consists of SPIDENB, SPICLK ,
SPIDIO, and SPIDO-(SPARE) (output in four-wire mode) signals. See Table 25 and Figure 25.
JTAG Interface
The GC533x includes a five-pin JTAG interface that supports boundary scan for all CMOS pads in the chip,
aside from the TESTMOD pin. The BBIN, BBOUT, RX, TX, and SYNC pins are all LVDS and do not get JTAG
boundary scan. IMPORTANT NOTE: if not using JTAG, the TRSTB signal should be grounded (or pulled to
ground through R ≤ 1 kΩ); otherwise, the JTAG port may take control of the pins. See Table 24 and Figure 24.
A BSDL file is available on the GC533x Web page.
Input and Output Syncs
The GC533x features two LVDS input syncs (SYNCA and SYNCB) and one LVDS output (SYNCOUT)
user-programmable sync. These are typically used as trigger/synchronization mechanisms to activate features
within the device. The input syncs can be used to trigger events such as:
• Power measurements
• DUC channel delay, mixer phase and dither
• Initializing/loading filter coefficients
• Capturing and sourcing of data in the capture buffers
• Controlling gating intervals for AGC and other adaptive loops
• Frequency NCO changes, or hopping synchronization
The SYNCA signal is used for device startup. The SYNCB signal can be used for shared feedback
synchronization between multiple GC533x devices. The sync signal is active-high. The width (number of positive
edges of the DPD clock) of the sync signal depends on the configuration. See the GC533x sync and MPU
application note to determine the proper sync duration. A typical sync-pulse duration is four DPD clocks. The
sync must be periodic, and usually starts at the beginning of the TX frame.
The output sync can be programmed to reflect triggering of specific events within the GC533x, and is primarily
used to output the capture-buffer sync out signal.
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