GC1012A Datasheet, PDF (28/30 Pages) Texas Instruments – DIGITAL TUNER CHIP

GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
5.7 EXAMPLE RECEIVER ARCHITECTURE
An example digital receiver architecture using the GC1012A chip is shown in Figure 7.
USER
INTERFACE
FROM
ANTENNAE
ANALOG
FRONT
END
ANALOG
TO
DIGITAL
CONVERTER
GC1012A
CHIP
DIGITAL
TO
ANALOG
CONVERTER
(OPTIONAL)
SIGNAL
OUT
Â¥ GAIN
Â¥ BANDLIMIT TO
30MHz OR LESS
Â¥ DOWNCONVERT
Â¥ OUTPUT IS
CENTERED AROUND
15MHz
Â¥ DIGITIZES TO 8, 10
OR 12 BITS
Â¥ 60 MHz SAMPLING
RATE
Â¥ TUNES TO
DESIRED
FREQUENCY
Â¥ NARROWBAND
FILTERS SIGNAL
Â¥ REDUCES
SAMPLE RATE
Â¥ CONVERTS BACK TO
ANALOG
Figure 7. Example Digital Receiver Architecture
The receiver contains an analog front end which downconverts up to 30MHz of radio spectrum to
an IF frequency around 15MHz¹. It also adjusts the gain of the signal so that it fills the dynamic range of the
analog to digital converter (ADC). The ADC digitizes the signal using up to 12 bits of resolution at a sampling
rate up to 60 MHZ. The GC1012A chip tunes, downconverts, and narrowband filters desired frequencies
from within the 30 MHz band. The GC1012A output can either be converted back to analog or kept in its
digital state for subsequent signal processing.
1. Note that the HF spectrum (1 to 30MHz) can be digitized directly.
GRAYCHIP,INC.
- 23 -
FEBRUARY 18, 1998
This document contains information which may be changed at any time without notice