GC1012A Datasheet, PDF (25/30 Pages) Texas Instruments – DIGITAL TUNER CHIP

GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
4.5 AC CHARACTERISTICS
Table 5: AC Characteristics (-40 TO +85^oC Ambient, unless noted)
PARAMETER
SYMBOL
3.3V +/- 5%
MIN MAX
5 V +/- 5%
MIN MAX
UNITS
NOTES
Clock Frequency
Clock low period (Below V_IL)
Clock high period (Above V_IH)
Data setup before CK goes high
(X, SS, AS or GS)
F_CK
t_CKL
t_CKH
t_SU
0.01
45
0.01
80
8
5
8
5
4
2
MHz
ns
ns
ns
2, 3, 4
1
1
1
Data hold time after CK goes high
Data output delay from rising edge of CK.
(I, Q, WS, IFLAG, OS, OFLOW, SO
t_HD
0
0
ns
1
t_DLY
2
13
2
9
ns
1, 5
Data to tristate delay
(I or Q to hiZ from OEI or OEQ)
t_DZ
2
5
2
5
1
Tristate to data output delay
(I or Q valid from OEI or OEQ)
t_ZD
3
13
3
9
ns
1, 5
Control Setup before CS goes low (A, R/W
t_CSU
10
10
during read, and A, R/W, C during write)
ns
1
Control hold after CS goes high (A, R/W during
t_CHD
10
10
read, and A, R/W, C during write)
ns
1
Control strobe (CS) pulse width
(Write operation)
t_CSPW
60
30
ns
1,6
Control output delay CS low to C
(Read Operation)
t_CDLY
120
90
ns
1,6
Control tristate delay after CS goes high
Quiescent supply current
(V_IN=0 or V_CC, F_CK = 1KHz)
Supply current
(F_CK =45MHz)
t_CZ
I_CCQ
I_CC
20
10
ns
1
200
200
uA
1
386
585
mA
1, 7
Notes:
1. Controlled by design and process and not directly tested. Verified on initial part evaluation.
2. Each part is tested at 25 deg C for the given specification.
3. Temperature range is verified by lot sampling.
4. The chip may not operate properly at clock frequencies below MIN and MAX.
5. Capacitive output load is 20pf. Delays are measured from the rising edge of the clock to the output level rising
above V_IH or Falling below V_IL.
6. Capacitive output load is 80pf.
7. Current changes linearly with voltage and clock speed.
Icc (MAX)
=
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V_----C_-5----C_---øö
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-4^F--5--^C--_M-^K--_øö
585mA
GRAYCHIP,INC.
- 20 -
FEBRUARY 18, 1998
This document contains information which may be changed at any time without notice