GC1012A Datasheet, PDF (14/30 Pages) Texas Instruments – DIGITAL TUNER CHIP

GC1012A DIGITAL TUNER
DATA SHEET REV 0.1
SIGNAL
X[0:11]
CK
SS
AS
GS
I[0:15]
OEI
Q[0:15]
OEQ
WS
IFLAG
SO
INT
OS
OFLOW
C[0:7]
A[0:3]
R/W
CS
DESCRIPTION
INPUT DATA. Active high
The 12 bit twoÕs complement input samples. New samples are clocked into the chip on the rising edge of the clock.
The input data rate is assumed to be equal to the clock rate.
CLOCK INPUT. Active high
The clock input to the chip. The X, SS, GS and AS signals are clocked into the chip on the rising edge of this clock.
The I, Q, WS, IFLAG, OS, OFLOW and SO signals are clocked out on the rising edge of this clock.
SYSTEM SYNC. Active low
The sync input to the chip. All timers, accumulators, and control counters are, or can be, synchronized to SS. Bits in
control register 4 (see Section 3.2) determine the operation of SS. This sync is clocked into the chip on the rising edge
of the clock.
ACCUMULATOR SYNC. Active low
The accumulator sync is provided to synchronously change tuning frequencies. This sync can be used to load a new
tuning frequency into the frequency register and/or to clear the frequency accumulator. This signal is clocked into the
chip on the rising edge of the clock.
GAIN SYNC. Active low
The gain sync is provided to synchronously change gain settings. This signal is clocked into the chip on the rising edge
of the clock.
IN-PHASE OUTPUT DATA. Active high
The I part of each complex output sample is output as a 16 bit word on this pin. The bits are clocked out on the rising
edge of the clock.
IN-PHASE OUTPUT ENABLE. Active low
The I[0:15] output pins are put into a high impedance state when this pin is high.
QUADRATURE OUTPUT DATA. Active high
The Q part of each complex output sample is output as a 16 bit word on this pin. The bits are clocked out on the rising
edge of the clock.
QUADRATURE OUTPUT ENABLE. Active low
The Q[0:15] output pins are put into a high impedance state when this pin is high.
WORD STROBE. Programmable active high or low level
This strobe is output synchronous with the I and Q data words. The strobe occurs once per bit and is either one clock
wide or has a 50% duty cycle. The high/low polarity of the strobe is programmable. See Section 3.5 for details.
IN-PHASE STROBE. Active high
This strobe identifies the in-phase half of a complex pair when the outputs are in the IQ_MUX mode. See Section 3.5
for details. This signal is high when the I-half is output and is low when the Q-half is output.
SYNC OUT. Active low
This signal is either a delayed version of the input system sync SS, or, if SS_MUX in control register 4 is set, is the
internally generated sync which has a period of 2²⁰ clocks.
INTERRUPT OUT. Active low
This signal is the READY flag from control register 9. This interrupt goes active when a new output sample is ready in
control registers 12, 13, 14, and 15.
ONE SHOT STROBE. Active low
This output is a one-shot sync strobe generated by writing to control address 10. The strobe is one clock cycle wide.
OVERFLOW FLAG. Active low
This signal goes low when an overflow is detected in the gain circuit. The signal will either pulse low for one clock cycle
or will stay low depending upon the state of the OFLOW_MODE bit in control register 9.
CONTROL DATA I/O BUS. Active high
This is the 8 bit control data I/O bus. Control register data is loaded into the chip or read from the chip through these
pins. The chip will only drive these pins when CS is low and R/W is high.
CONTROL ADDRESS BUS. Active high
These pins are used to address the 16 control registers within the chip. Each of the 16 control registers within the chip
are assigned a unique address. A control register can be written to or read from by setting A[0:3] to the registerÕs
address.
READ/WRITE CONTROL. High for read, low for write
This pin determines if the control bus cycle is a read or write operation. The pin is high for a read and is low for a write.
CONTROL STROBE. Active low
This control strobe enables the read or write operation. The contents of the register selected by A[0:3] will be output
on C[0:7] when R/W is high and CS is low. If R/W is low when CS goes low, then the selected register will be loaded
with the contents of C[0:7].
GRAYCHIP,INC.
-9-
FEBRUARY 18, 1998
This document contains information which may be changed at any time without notice