CC2480_11 Datasheet, PDF (28/48 Pages) Texas Instruments – Z-Accel 2.4 GHz ZigBee Processor

CC2480
9.5 USART
The USART is a serial communications
interface that can be operated in either
9.5.1 UART mode
For asynchronous serial interfaces, the UART
mode is provided. In the UART mode the
interface uses a two-wire or four-wire interface
consisting of the pins RXD, TXD and optionally
RTS and CTS. The UART mode of operation
is as follows:
• Baud rate: 115200.
• Hardware (RTS/CTS) flow control.
asynchronous UART mode or in synchronous
SPI mode.
• 8N1 byte format.
• DCE signal connection.
The UART mode provides full duplex
asynchronous transfers, and the
synchronization of bits in the receiver does not
interfere with the transmit function. A UART
byte transfer consists of a start bit, eight data
bits, a parity bit, and one stop bit.
9.5.2 SPI Mode
This section describes the SPI mode of
operation for synchronous communication. In
SPI mode, the USART communicates with an
external system through a 3-wire or 4-wire
interface. The interface consists of the pins SI,
SO, SCK and SS_N. The SPI mode is as
follows:
9.5.2.1
SPI Slave Operation
An SPI byte transfer in slave mode is
controlled by the external system. The data on
the SI input is shifted into the receive register
controlled by the serial clock SCK which is an
9.5.3 SSN Slave Select Pin
When the USART is operating in SPI mode,
configured as an SPI slave, a 4-wire interface
is used with the Slave Select (SSN) pin as an
input to the SPI (edge controlled). At falling
edge of SSN the SPI slave is active and
receives data on the SI input and outputs data
on the SO output. At rising edge of SSN, the
SPI slave is inactive and will not receive data.
• SPI slave.
• Clock speed up to 4 MHz.
• Clock polarity 0 and clock phase 0 on
CC2480 .
• Bit order: MSB first.
input in slave mode. At the same time the byte
in the transmit register is shifted out onto the
SO output.
Note that the SO output is not tri-stated after
rising edge on SSn. This could be achieved
using an external buffer. Also note that release
of SSn (rising edge) must be aligned to end of
byte recived or sent. If released in a byte the
next received byte will not be received
properly as information about previous byte is
present in SPI system.
CC2480 Data Sheet SWRS074
Page 28 of 43