BQ2084-V133 Datasheet, PDF (28/64 Pages) Texas Instruments – SBS v1.1-COMPLIANT GAS GAUGE FOR USE WITH THE bq29312

bq2084-V133
SLUS640A – JUNE 2005 – REVISED JUNE 2005
www.ti.com
SMBus
The SMBus interface is a command-based protocol. A processor acting as the bus master initiates
communication to the bq2084-V133 by generating a start condition. A start condition consists of a high-to-low
transition of the SMBD line while the SMBC is high. The processor then sends the bq2084-V133 device address
of 0001011 (bits 7-1) plus a R/W bit (bit 0) followed by an SMBus command code. The R/W bit (LSB) and the
command code instruct the bq2084-V133 to either store the forthcoming data to a register specified by the
SMBus command code or output the data from the specified register. The processor completes the access with a
stop condition. A stop condition consists of a low-to-high transition of the SMBD line while the SMBC is high.
With SMBus, the most-significant bit (MSB) of a data byte is transmitted first. In some instances, the
bq2084-V133 acts as the bus master. This occurs when the bq2084-V133 broadcasts charging requirements and
alarm conditions to device addresses 0x12 (SBS Smart Charger) and 0x10 (SBS Host Controller.)
SMBus Protocol
The bq2084-V133 supports the following SMBus protocols:
• Read word
• Write word
• Block read
A processor acting as the bus master uses the three protocols to communicate with the bq2084-V133. The
bq2084-V133 acting as the bus master uses the write word protocol.
The SMBD and SMBC pins are open drain and require external pullup resistors. A 1-MΩ pulldown resistor in the
battery pack on SMBC and SMBD is required to ensure the detection of the SMBus off-state, the performance of
automatic offset calibration, and the initiation of the low-power sleep mode when the battery pack is removed.
SMBus Packet Error Checking
The bq2084-V133 supports packet error checking as a mechanism to confirm proper communication between it
and another SMBus device. Packet error checking requires that both the transmitter and receiver calculate a
packet error code (PEC) for each communication message. The device that supplies the last byte in the
communication message appends the PEC to the message. The receiver compares the transmitted PEC to its
PEC result to determine if there is a communication error.
PEC Protocol
The bq2084-V133 can receive or transmit data with or without PEC. Figure 5 shows the communication protocol
for the read word, write word, and read block messages without PEC. Figure 6 includes PEC.
In the read word protocol, the bq2084-V133 receives the PEC after the last byte of data from the host. If the host
does not support PEC, the last byte of data is followed by a stop condition. After receipt of the PEC, the
bq2084-V133 compares the value to its calculation. If the PEC is correct, the bq2084-V133 responds with an
ACKNOWLEDGE (ACK). If it is not correct, the bq2084-V133 responds with a NOT ACKNOWLEDGE (NACK)
and sets an error code. In the write word and block read, the host generates an ACK after the last byte of data
sent by the bq2084-V133. The bq2084-V133 then sends the PEC and the host acting as a master-receiver
generates a NACK and a stop condition.
28