PCI2031 Datasheet, PDF (27/70 Pages) Texas Instruments – PCI-TO-PCI BRIDGE

PCI2031
PCI-TO-PCI BRIDGE
SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998
latency timer register
Bit
7
6
5
4
3
2
1
0
Name
Latency timer
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Default
0
0
0
0
0
0
0
0
Register: Latency timer
Type:
Read/write
Offset:
0Dh
Default: 00h
Description: The latency timer register specifies the latency timer for the bridge in units of PCI clock cycles.
When the bridge is a primary PCI bus initiator and asserts P_FRAME, the latency timer begins
counting from 0. If the latency timer expires before the bridge transaction has terminated, the
bridge terminates the transaction when its P_GNT is deasserted.
header type register
Bit
7
6
5
4
3
2
1
0
Name
Type
Header type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
1
Register: Header type
Type:
Read only
Offset:
0Eh
Default: 01h
Description: The header type register is read only and returns 01h when read, indicating that the PCI2031
configuration space adheres to the PCI-to-PCI bridge configuration. Only the layout for bytes
10h–3Fh of configuration space is considered.
BIST register
Bit
7
6
5
4
3
2
1
0
Name
BIST
Type
R
R
R
R
R
R
R
R
Default
0
0
0
0
0
0
0
0
Register: BIST
Type:
Read only
Offset:
0Fh
Default: 00h
Description: The PCI2031 does not support built-in self test (BIST). The BIST register is read only and
returns the value 00h when read.
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