PCI2031 Datasheet, PDF (20/70 Pages) Texas Instruments – PCI-TO-PCI BRIDGE

PCI2031
PCI-TO-PCI BRIDGE
SCPS017A – DECEMBER 1997 – REVISED JANUARY 1998
slot numbers and chassis numbers (continued)
In a network server system, where the server might have multiple connections to several storage subsystems
and LAN segments, identifying a particular device in the network can be difficult. A server might contain several
PCI expansion slots, some of which contain multiple controllers. In this case, it is more difficult to identify a
particular chassis and slot within the chassis that contains a specific controller. In such a server system, if a
controller fails, software must have a way to determine which device failed and communicate this to the system
administrator so it can be replaced.
At power on, the system configuration software assigns each subsystem cabinet a chassis number. The network
controllers (e.g., a PCI Ethernet controller) are also identified by slot number. The host server is assigned
chassis 0. The chassis number register in the PCI2031 contains an 8-bit number that designates the chassis
number in which the slots on its secondary bus reside. Multiple PCI buses in the same chassis are assigned
the same number.
For more information, refer to the chapter “Where Do I Plug the Cable?” in the PCI Spring Developers’
Conference and Expo Conference Proceedings published by Annabooks, ISBN 0-929392-34-5.
PCI power management
The PCI power management specification establishes the infrastructure required to let the operating system
control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage
the power of PCI functions on the bus. The PCI bus and the PCI functions can be assigned one of four software
visible power management states, which result in varying levels of power savings.
The four power management states of PCI functions are D0 “Fully on” state, D1, D2 “intermediate states” and
D3 “Off” state. Similarly, bus power states of the PCI bus are B0–B3. The Bus power states B0–B3 are derived
from the device power state of the originating PCI2031 device.
For the operating system to power manage the device power states on the PCI bus, the PCI function supports
four power management operations:
D Capabilities reporting
D Power status reporting
D Setting the power state
D System wake–up
The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The
presence of new capabilities is indicated by a bit in the PCI status register and by providing a access to a
capabilities list.
behavior in low power states
The PCI2031 supports D0, D1, D2, D3 cold, and D3 hot power states. The PCI2031 is fully functional only in
D0 state. In the lower power states, the bridge does not accept any memory or I/O transactions. These
transactions are aborted by the master. The bridge accepts Type 0 configuration cycles in all power states
except D3 cold. The bridge also accepts Type 1 configuration cycles but does not pass these cycles to the
secondary bus in any of the lower power states. Type 1 configuration writes are discarded and reads return all
1’s. All error reporting is done in the low power states. When in D2 and D3 hot states, the bridge turns off all
secondary clocks for further power savings.
When going from D3 hot to D0, an internal reset is generated. This reset initializes all PCI configuration registers
to their default values. All TI specific registers (40h – FFh) are not reset. Power Management registers are also
not reset.
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