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MSP430F147 Datasheet, PDF (27/59 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER | |||
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MSP430x13x, MSP430x14x, MSP430x14x1
MIXED SIGNAL MICROCONTROLLER
SLAS272F â JULY 2000 â REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs â Ports P1, P2, P3, P4, P5, and P6
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
IOH(max) = â1 mA, VCC = 2.2 V, See Note 1 VCCâ0.25
VCC
VOH High-level output voltage
IOH(max) = â6 mA,
IOH(max) = â1 mA,
VCC = 2.2 V,
VCC = 3 V,
See Note 2
See Note 1
VCCâ0.6
VCCâ0.25
VCC
V
VCC
IOH(max) = â6 mA, VCC = 3 V,
See Note 2
VCCâ0.6
VCC
IOL(max) = 1.5 mA, VCC = 2.2 V, See Note 1
VSS
VSS+0.25
VOL Low-level output voltage
IOL(max) = 6 mA,
IOL(max) = 1.5 mA,
VCC = 2.2 V,
VCC = 3 V,
See Note 2
See Note 1
VSS
VSS
VSS+0.6
V
VSS+0.25
IOL(max) = 6 mA,
VCC = 3 V,
See Note 2
VSS
VSS+0.6
NOTES:
1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±6 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±24 mA to satisfy the maximum
specified voltage drop.
output frequency
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
fTAx
fACLK,
fMCLK,
fSMCLK
tXdc
TA0..2, TB0âTB6,
Internal clock source, SMCLK signal
applied (see Note 1)
CL = 20 pF
P5.6/ACLK, P5.4/MCLK, P5.5/SMCLK CL = 20 pF
Duty cycle of output frequency,
P2.0/ACLK
CL = 20 pF,
VCC = 2.2 V / 3 V
P1.4/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
fACLK = fLFXT1 = fXT1
fACLK = fLFXT1 = fLF
fACLK = fLFXT1/n
fSMCLK = fLFXT1 = fXT1
fSMCLK = fLFXT1 = fLF
fSMCLK = fLFXT1/n
fSMCLK = fDCOCLK
DC
fSystem
MHz
fSystem
40%
30%
40%
35%
50%â
15 ns
50%â
15 ns
50%
50%
50%
60%
70%
60%
65%
50%â
15 ns
50%â
15 ns
NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK
frequencies can be different.
⢠POST OFFICE BOX 655303 DALLAS, TEXAS 75265
27
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