MSP430F147 Datasheet, PDF (26/59 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430x13x, MSP430x14x, MSP430x14x1
MIXED SIGNAL MICROCONTROLLER
SLAS272F − JULY 2000 − REVISED JUNE 2004
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6
PARAMETER
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys Input voltage hysteresis (VIT+ − VIT−)
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
MIN TYP MAX UNIT
1.1
1.5
V
1.5
1.9
0.4
0.9
V
0.90
1.3
0.3
1.1
V
0.5
1
standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
MIN
VIL Low-level input voltage
VIH High-level input voltage
VCC = 2.2 V / 3 V
VSS
0.8×VCC
TYP
MAX
VSS+0.6
VCC
UNIT
V
V
inputs Px.x, TAx, TBx
PARAMETER
t(int)
External interrupt timing
t(cap)
Timer_A, Timer_B capture
timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
TA0, TA1, TA2
TB0, TB1, TB2, TB3, TB4, TB5, TB6 (see
Note 2)
VCC
2.2 V/3 V
2.2 V
3V
2.2 V
3V
MIN TYP MAX UNIT
1.5
cycle
62
ns
50
62
ns
50
f(TAext)
f(TBext)
Timer_A, Timer_B clock
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L)
2.2 V
3V
8
MHz
10
f(TAint)
f(TBint)
NOTES:
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
2.2 V
3V
8
MHz
10
1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with
trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in
MCLK cycles.
2. Seven capture/compare registers in ’x14x(1) and three capture/compare registers in ’x13x.
leakage current (see Note 1)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
Ilkg(P1.x) _Leakage
Port P1 V(P1.x) (see Note 2)
±50
Ilkg(P2.x) current (see
Port P2 V(P2.3) V(P2.4) (see Note 2)
VCC = 2.2 V/3 V
±50
Ilkg(P6.x) ^{Note 1)}
Port P6 V(P6.x) (see Note 2)
±50
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.
UNIT
nA
26
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