THS4211 Datasheet, PDF (25/41 Pages) Texas Instruments – LOW-DISTORTION HIGH-SPEED VOLTAGE FEEDBACK AMPLIFIER

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R_S
E_RS
E_NI
I_BN
THS4211/THS4215
+
E_O
_
4kTR_S
R_f
E_RF
4kT
R_g
I_BI
4kTR_f
R_g
4kT = 1.6E-20J
at 290K
Figure 87. Noise Analysis Model
The total output shot noise voltage can be computed
as the square of all square output noise voltage
contributors. Equation 4 shows the general form for
the output noise voltage using the terms shown in
Equation 4:
Ǹǒ Ǔ E_O +
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S NG² ) ^ǒI_BIR_f^Ǔ2 ) 4kTR_fNG
(4)
Dividing this expression by the noise gain (NG=(1+
R_f/R_g)) gives the equivalent input-referred spot noise
voltage at the noninverting input, as shown in
Equation 5:
Ǹ ǒ Ǔ _{EO +}
2
E_NI2 ) ^ǒI_BNR_S^Ǔ2 ) 4kTR_S )
I_BIR_f
NG
)
4kTR_f
NG
(5)
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
A high-speed, high open-loop gain amplifier like the
THS4211 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin.
When the amplifier's open-loop output resistance is
considered, this capacitive load introduces an ad-
ditional pole in the signal path that can decrease the
phase margin. When the primary considerations are
frequency response flatness, pulse response fidelity,
or distortion, the simplest and most effective solution
is to isolate the capacitive load from the feedback
loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This
does not eliminate the pole from the loop response,
but rather shifts it and adds a zero at a higher
frequency. The additional zero acts to cancel the
phase lag from the capacitive load pole, thus increas-
ing the phase margin and improving stability.
THS4211
THS4215
SLOS400D – SEPTEMBER 2002 – REVISED NOVEMBER 2004
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4211. Long PC board traces,
unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4211 output pin (see Board Layout
Guidelines).
The criterion for setting this R_(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load. For a gain of +2, the frequency response at the
output pin is already slightly peaked without the
capacitive load, requiring relatively high values of
R_(ISO) to flatten the response at the load. Increasing
the noise gain also reduces the peaking.
FREQUENCY RESPONSE
vs
CAPACITIVE LOAD
1
R_(ISO) = 10 Ω
0.5
C_L = 100 pF
V_S =±5 V
0
-0.5
-1
-1.5
-2
R_(ISO) = 15 Ω
C_L = 50 pF
R_(ISO) = 25 Ω
C_L = 10 pF
-2.5
-3
100 k
1M
10 M
100 M
1G
Capacitive Load - Hz
Figure 88. Isolation Resistor Diagram
BOARD LAYOUT
Achieving optimum performance with a high fre-
quency amplifier like the THS4211 requires careful
attention to board layout parasitics and external
component types.
Recommendations that optimize performance include
the following:
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it
can react with the source impedance to cause
unintentional band limiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on
the board.
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