LT1054_15 Datasheet, PDF (24/33 Pages) Linear Technology – Switched-Capacitor Voltage Converter with Regulator

LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015
10 Layout
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10.1 Layout Guidelines
• Try to run the feedback trace as far from the noisy power or clocking traces as possible. In the case that the
OSC pin is not being used, as in Figure 31, the FB trace can be ran on a lower layer under the OSC pin.
When OSC is being utilized by a noisy clocking signal, it is recommended to run the FB trace on a lower layer
through the Vref pin.
– Keep the FB trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-
off, but keeping it away from EMI and other noise sources is the more critical of the two.
• Keep the external capacitor traces short, specifically on the CAP+ and CAP- nodes that have the fastest rise
and fall times.
• Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a
standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.
10.2 Layout Example
2.0 2F
Ground
FB/SD 1
CAP+ 2
Ground _{GND 3}
10 2F _{&$3í 4}
8 V_CC
7 OSC
6 V_REF
5 V_OUT
Positive Supply
R1
R2
0.002 2F
100 2F
Ground
Figure 31. Basic Inverter/Regulator Layout
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