BQ24152 Datasheet, PDF (24/38 Pages) Texas Instruments – Fully Integrated Switch-Mode One-Cell Li-Ion Charger with Full USB Compliance and USB-OTG Support

bq24152
SLUS847 – JUNE 2008 ...................................................................................................................................................................................................... www.ti.com
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 30). This releases the bus and stops the communication
link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I²C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this
section will result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
Not Acknowledge
Acknowledge
SCL From
Master
START
Condition
1
2
8
Figure 29. Acknowledge on the I²C Bus™
9
Clock Pulse for
Acknowledgement
Recognize START or
REPRATED START
Condition
SDA
MSB
Address
Generate ACKNOWLEDGE
Signal
Acknowledgement
Signal From Slave
Recognize STOP or
REPRATED START
Condition
P
Sr
R/W
SCL
S
or
Sr
ACK
Clock Line Held Low While
Interrupts are Serviced
Figure 30. Bus Protocol
Sr
ACK
or
P
H/S Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'.
This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation
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