ADC081C027CIMK Datasheet, PDF (24/41 Pages) National Semiconductor (TI) – ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter (ADC) with Alert Function

ADC081C021, ADC081C027
SNAS447C – FEBRUARY 2008 – REVISED MARCH 2013
www.ti.com
High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communication differs slightly from Standard-Fast mode.
Figure 26 describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master
generates a Start condition and sends the 8-bit Hs master code (00001XXX) to the ADC081C021. Next, the
ADC081C021 responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to
Hs-mode by increasing the bus speed and generating a second Repeated Start condition (driving SDA low while
SCL is pulled high). At this point, the master sends the slave address to the ADC081C021, and communication
continues as shown above in the "Basic Operation" Diagram (see Figure 25).
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode
again before increasing the bus speed and switching to Hs-mode.
SDA
SCL
START
NACK
8-ELW 0DVWHU FRGH ³00001[[[´
Not-Acknowledge
from the Device
1
2
5
6
7
8
9
Standard-Fast Mode
Repeated
START
Figure 26. Beginning Hs-Mode Communication
MSB
7-bit Slave
Address
12
Hs-Mode
I²C Slave (Hardware) Address
The ADC has a seven-bit hardware address which is also referred to as a slave address. For the VSSOP-8
version of the ADC081C021, this address is configured by the ADR0 and ADR1 addres selection inputs. For the
ADC081C027, the address is configured by the ADR0 address selection input. ADR0 and ADR1 can be
grounded, left floating, or tied to V_A. If desired, ADR0 can be set to V_A/2 rather than left floating. The state of
these inputs sets the hardware address that the ADC responds to on the I²C bus (see Table 2). For the SOT-6
version of the ADC081C021, the hardware address is not pin-configurable and is set to 1010100. The diagrams
in COMMUNICATING WITH THE ADC081C021 describe how the I²C controller should address the ADC via the
I²C interface.
Pin compatible alternatives that provide additional address options to the SOT-6 version of the ADC081C021 and
the ADC081C027 are available.
Slave Address
[A6 - A0]
1010000
1010001
1010010
1010100
1010101
1010110
1011000
1011001
1011010
Table 2. Slave Addresses
ADC081C027
(SOT-6)
ADR0
Floating
GND
V_A
-----------------
-----------------
-----------------
-----------------
-----------------
-----------------
ADC081C021
(SOT-6)
ALERT
-----------------
-----------------
-----------------
Single Address
-----------------
-----------------
-----------------
-----------------
-----------------
ADR1
Floating
Floating
Floating
GND
GND
GND
V_A
V_A
V_A
ADC081C021
(VSSOP-8)
ADR0
Floating
GND
V_A
Floating
GND
V_A
Floating
GND
V_A
24
Submit Documentation Feedback
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: ADC081C021 ADC081C027