ADC081C027CIMK Datasheet, PDF (20/41 Pages) National Semiconductor (TI) – ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter (ADC) with Alert Function

ADC081C021, ADC081C027
SNAS447C – FEBRUARY 2008 – REVISED MARCH 2013
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Bits
Name
7:5
Cycle Time
4
Alert Hold
3
Alert Flag Enable
2
Alert Pin Enable
1
Reserved
0
Polarity
Description
Configures Automatic Conversion mode. When these bits are set to zeros, the automatic conversion
mode is disabled. This is the case at power-up.
When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion
mode. (See AUTOMATIC CONVERSION MODE). The Cycle Time table shows how different values
provide various conversion intervals.
0: Alerts will self-clear when the measured voltage moves within the limits by more than the hysteresis
register value.
1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the alert
low flag in the Alert Status register.
0: Disables alert status bit [D15] in the Conversion Result register.
1: Enables alert status bit [D15] in the Conversion Result register.
0: Disables the ALERT output pin. The ALERT output will TRI-STATE when the pin is disabled.
1: Enables the ALERT output pin.
*This bit does not apply to the ADC081C027.
Always reads zeros. Zeros must be written to these bits.
This bit configures the active level polarity of the ALERT output pin.
0: Sets the ALERT pin to active low.
1: Sets the ALERT pin to active high.
*This bit does not apply to the ADC081C027.
V_LOW -- Alert Limit Register - Under Range
This register holds the lower limit threshold used to determine the alert condition. If the conversion moves lower
than this limit, a V_LOW alert is generated.
Pointer Address 03h (Read/Write)
Default Value: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
Reserved
V_LOW Limit [7:4]
D7
D6
D5
D4
D3
D2
D1
D0
V_LOW Limit [3:0]
Reserved
Bits
15:12
11:4
3:0
Name
Reserved
V_LOW Limit
Reserved
Description
Always reads zeros. Zeros must be written to these bits.
Sets the lower limit threshold used to determine the alert condition. If the conversion moves lower than
this limit, a V_LOW alert is generated.
Always reads zeros. Zeros must be written to these bits.
V_HIGH -- Alert Limit Register - Over Range
This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher
than this limit, a V_HIGH alert is generated.
Pointer Address 04h (Read/Write)
Default Value: 0FFFh
D15
D14
D13
D12
D11
D10
D9
D8
Reserved
V_HIGH Limit [7:4]
D7
D6
D5
D4
D3
D2
D1
D0
V_HIGH Limit [3:0]
Reserved
20
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