ADC081C027CIMK Datasheet, PDF (23/41 Pages) National Semiconductor (TI) – ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter (ADC) with Alert Function

ADC081C021, ADC081C027
www.ti.com
SNAS447C – FEBRUARY 2008 – REVISED MARCH 2013
All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop
condition occurs when SDA is pulled high while SCL is high. After a Stop condition, the bus remains idle until a
master generates another Start condition.
Please refer to the Philips I2C^® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial
interface.
SDA
MSB
SCL
1
START or
REPEATED
START
7-bit Slave Address
2
6
LSB
ACK
R/W
Direction
Bit
Acknowledge
from the Device
MSB
7
8
9
1
Data Byte
2
LSB N/ACK
*Acknowledge
or Not-ACK
8
9
Repeated for the Lower Data Byte
and Additional Data Transfers
STOP
*Note: In continuous mode, this bit must be an ACK from
the data receiver. Immediately preceding a STOP
condition, this bit must be a NACK from the master.
Figure 25. Basic Operation.
Standard-Fast Mode
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is
high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have
been transmitted by the master, SDA is released by the master and the ADC081C021 either ACKs or NACKs the
address. If the slave address matches, the ADC081C021 ACKs the master. If the address doesn't match, the
ADC081C021 NACKs the master.
For a write operation, the master follows the ACK by sending the 8-bit register address pointer to the ADC. Then
the ADC081C021 ACKs the transfer by driving SDA low. Next, the master sends the upper 8-bits to the
ADC081C021. Then the ADC081C021 ACKs the transfer by driving SDA low. For a single byte transfer, the
master should generate a stop condition at this point. For a 2-byte write operation, the lower 8-bits are sent by
the master. The ADC081C021 then ACKs the transfer, and the master either sends another pair of data bytes,
generates a Repeated Start condition to read or write another register, or generates a Stop condition to end
communication.
A read operation can take place either of two ways:
If the address pointer is pre-set before the read operation, the desired register can be read immediately following
the slave address. In this case, the upper 8-bits of the register, set by the pre-set address pointer, are sent out
by the ADC. For a single byte read operation, the Master sends a NACK to the ADC and generates a Stop
condition to end communication after receiving 8-bits of data. For a 2-Byte read operation, the Master continues
the transmission by sending an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC register.
At this point, the master either sends; an ACK to receive more data or, a NACK followed by a Stop or Repeated
Start. If the master sends an ACK, the ADC sends the next upper data byte, and the read cycle repeats.
If the ADC081S021 address pointer needs to be set, the master needs to write to the device and set the address
pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit,
the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 30).
Following this sequence, the ADC sends out the upper 8-bits of the register. For a single byte read operation, the
Master must then send a NACK to the ADC and generate a Stop condition to end communication. For a 2-Byte
write operation, the Master sends an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC
register. At this point, the master sends either an ACK to receive more data, or a NACK followed by a Stop or
Repeated Start. If the master sends an ACK, the ADC sends another pair of data bytes, and the read cycle will
repeat. The number of data words that can be read is unlimited.
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