TLV320AIC3204 Datasheet, PDF (23/159 Pages) Texas Instruments – Ultra Low Power Stereo Audio Codec

TLV320AIC3204
www.ti.com
Pin Function
L
General Purpose Input II
L
General Purpose Input III
M
INT1 output
N
INT2 output
O
Digital Microphone Data Input
P
Digital Microphone Clock Output
Q
Secondary I²S BCLK input
R
Secondary I²S WCLK in
S
Secondary I²S DIN
T
Secondary I²S DOUT
U
Secondary I²S BLCK OUT
V
Secondary I²S WCLK OUT
W
Headset Detect Input
X
Aux Clock Output
1
MCLK
Ultra Low Power Stereo Audio Codec
SLOS602A – SEPTEMBER 2008 – REVISED OCTOBER 2008
2
3
4
BCLK WCLK DIN
MFP1
5
DOUT
MFP2
8
SCLK
MFP3
E
11
MISO
MFP4
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
32
GPIO
MFP5
E
E
E
E
E
E
E
E
E
E
E
5.2.6 Register Settings for Multifunction Pins
The table below summarizes the multifunction pin specific settings that must be applied. Please be aware
that more settings may be necessary to obtain a full interface definition matching the application
requirement (e.g. registers Pg1 Reg 32 and 33).
Description
Required Register Setting
A1
PLL Input on pin 1, MCLK Pg 0, Reg 4, D(3:2)=00
A2
PLL Input on pin 2, BCLK Pg 0, Reg 4, D(3:2)=01
A4
PLL Input on pin 4,
DIN/MFP1
Pg 0, Reg 54, D(2:1)=01
Pg 0, Reg 4, D(3:2)=11
A32
PLL Input on pin 32,
GPIO/MFP5
Pg 0, Reg 52, D(5:2)=0001
Pg 0, Reg 4, D(3:2)=10
B1
Codec Clock Input on pin 1,
MCLK
Pg 0, Reg 4, D(1:0)=00
B2
Codec Clock Input on pin 2,
BCLK
Pg 0, Reg 4, D(1:0)=01
B32
Codec Clock Input on pin
32, GPIO/MPF5
Pg 0, Reg 52, D(5:2)=0001
Pg 0, Reg 4, D(1:0)=10
C2
I²S BCLK input on pin 2,
BCLK
Pg 0, Reg 27, D(3)=0
D2
I²S BCLK output on pin 2,
BCLK
Pg 0, Reg 27, D(3)=1
E3
I²S WCLK input on pin 3,
WCLK
Pg 0, Reg 27, D(2)=0
F3
I²S WCLK output on pin3,
WCLK
Pg 0, Reg 27, D(2)=1
Description
Required Register
Setting
N5
INT2 output on pin 5, DOUT/MFP2
Pg 0, Reg
53,D(3:1)=101
N11
INT2 output on pin 11,
MISO/MFP4
Pg 0, Reg 55,
D(4:1)=0101
N32
INT2 output on pin 32,
GPIO/MFP5
Pg 0, Reg 52,
D(5:2)=0110
Pg 0, Reg 54,
O4
Digital Microphone Data Input on D(2:1)=01
pin 4, DIN/MFP1
Pg 0, Reg 81,
D(5:4)=10
Pg 0, Reg 56,
O8
Digital Microphone Data Input on D(2:1)=01
pin 8, SCLK/MFP3
Pg 0, Reg 81,
D(5:4)=01
Pg 0, Reg 52,
O32
Digital Microphone Data Input on
pin 32, GPIO/MFP5
D(5:2)=0001
Pg 0, Reg 81,
D(5:4)=00
P11
Digital Microphone Clock Output
on pin 11, MISO/MFP4
Pg 0, Reg 55,
D(4:1)=0111
P32
Digital Microphone Clock Output
on pin 32, GPIO/MFP5
Pg 0, Reg 52,
D(5:2)=1010
Q8
Secondary I²S BCLK input on pin
8, SCLK/MFP3
Pg 0, Reg 56,
D(2:1)=01
Pg 0, Reg 31,6:5)=01
Q32
Secondary I²S BCLK input on pin
32, GPIO/MFP5
Pg 0, Reg 52,
D(5:2)=0001
Pg 0, Reg 31,6:5)=00
Pg 0, Reg 56,
R8
Secondary I²S WCLK in on pin 8, D(2:1)=01
SCLK/MFP3
Pg 0, Reg 31,
D(4:3)=01
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Application Information
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