ADS1118_13 Datasheet, PDF (23/38 Pages) Texas Instruments – Ultra-Small, Low-Power, SPI™-Compatible, 16-Bit Analog-to-Digital Converter and Temperature Sensor with Internal Reference

ADS1118
www.ti.com
SBAS457C – OCTOBER 2010 – REVISED FEBRUARY 2013
DATA RETRIEVAL
Data can be written to and read from the ADS1118 in the same manner in single-shot mode as in continuous
conversion mode, without having to issue any commands. The mode in which ADS1118 operates in can be
selected by the MODE bit in the Config register. Setting the MODE bit to '0' puts the device in continuous
conversion mode. In this mode, the device is constantly starting new conversions even when CS is high. When
configured for single-shot mode by setting the MODE bit to '1,' a new conversion only starts by writing a '1' to the
SS bit.
The conversion data are always buffered, and retain the current data until replaced by new conversion data.
Therefore, data can be read at any time without concern of data corruption. When DOUT/DRDY asserts low,
indicating that new conversion data are ready, the conversion data are read by shifting the data out on
DOUT/DRDY. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first SCLK rising edge. At the
same time that the conversion result is clocked out of DOUT/DRDY, new Config register data are latched on DIN
on the SCLK falling edge.
The ADS1118 also offers the possibility of direct readback of the Config register settings in the same data
transmission cycle. One complete data transmission cycle consists of either 32 bits (when the Config register
data readback is used) or 16 bits. The short 16-bit cycle can only be used when the CS line can be controlled
and is not permanently tied low.
32-Bit Data Transmission Cycle
As shown in Figure 44, the data in a 32-bit data transmission cycle consists of four bytes: two bytes for the
conversion result and an additional two bytes for the Config register readback. The MSB is always read first.
Direct Config register data readback is only functional for the first two bytes that are written to the device in a
data transmission cycle. Therefore, TI recommends writing the same Config register setting twice during one
cycle.
CS⁽¹⁾
SCLK
1
9
17
25
Hi-Z
DOUT/DRDY
DATA MSB DATA LSB CONFIG MSB CONFIG LSB
Next Data Ready
DIN
CONFIG MSB CONFIG LSB CONFIG MSB CONFIG LSB
(1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available.
Figure 44. 32-Bit Data Transmission Cycle with Config Register Readback
Alternatively, DIN can be held either low or high for the second half of the data transmission cycle, as shown in
Figure 45. When the ADS1118 is configured for continuous conversion mode by setting the MODE bit to '0', DIN
can even be held either low or high for the entire transmission cycle as well if no changes to the device setup
must be made.
CS⁽¹⁾
SCLK
Hi-Z
DOUT/DRDY
1
9
17
25
DATA MSB DATA LSB CONFIG MSB CONFIG LSB
Next Data Ready
DIN
CONFIG MSB CONFIG LSB
(1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available.
Figure 45. 32-Bit Data Transmission Cycle: DIN Held Low
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