ADS1118_13 Datasheet, PDF (20/38 Pages) Texas Instruments – Ultra-Small, Low-Power, SPI™-Compatible, 16-Bit Analog-to-Digital Converter and Temperature Sensor with Internal Reference

ADS1118
SBAS457C – OCTOBER 2010 – REVISED FEBRUARY 2013
www.ti.com
SERIAL INTERFACE
The SPI-compatible serial interface consists of either four signals (CS, SCLK, DIN, and DOUT/DRDY), or three
signals (in which case CS may be tied low). The interface is used to read conversion data, read and write
registers, and control device operation.
CHIP SELECT (CS)
The chip select (CS) selects the ADS1118 for SPI communication. This feature is useful when multiple devices
share the same serial bus. CS must remain low for the duration of the serial communication. When CS is taken
high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state,
DOUT/DRDY cannot provide data ready indication. In situations where multiple devices are present and
DOUT/DRDY must be monitored, CS must be periodically lowered. At this point, the DOUT/DRDY pin either
immediately goes high to indicate that no new data are available, or DOUT/DRDY immediately goes low to
indicate that new data are present in the Conversion register and are available for transfer. New data can be
transferred at any time without concern of data corruption. When a transmission starts, the current result is
locked into the output shift register and does not change until the communication completes. This system avoids
any possibility of data corruption. If the ADS1118 does not share the serial bus with another device, CS may be
tied low.
SERIAL CLOCK (SCLK)
The serial clock (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and
DOUT/DRDY pins into and out of the ADS1118. Even though the input has hysteresis, TI recommends keeping
SCLK as clean as possible to prevent glitches from accidentally shifting the data. If SCLK is held low for 28 ms,
the serial interface resets and the next SCLK pulse starts a new communication cycle. This timeout feature can
be used to recover communication when a serial interface transmission is interrupted. When the serial interface
is idle, hold SCLK low.
DATA INPUT (DIN)
The data input pin (DIN) is used along with SCLK to send data to the ADS1118. The device latches data on DIN
on the SCLK falling edge. The ADS1118 never drives the DIN pin.
DATA OUTPUT AND DATA READY (DOUT/DRDY)
The data output and data ready pin (DOUT/DRDY) is used with SCLK to read conversion and register data from
the ADS1118. DOUT/DRDY is also used to indicate that a conversion is completed and new data are available.
This pin transitions low when new data are ready for retrieval. The data ready signal can be used to trigger a
microcontroller to start reading data from the ADS1118. Data on DOUT/DRDY are shifted out on the SCLK rising
edge. In continuous conversion mode, DOUT/DRDY transitions high again 8 µs before the next data ready signal
(when DOUT/DRDY asserts low) if no data are retrieved from the device. This transition is shown in Figure 43.
Data transmission must complete before DOUT/DRDY automatically returns high. By default, DOUT/DRDY is
configured with a weak pull-up resistor if CS is high. This feature is intended to reduce the risk of DOUT/DRDY
floating near midsupply and causing leakage current in the master device. Alternatively, the ADS1118
DOUT/DRDY pin can be configured in the Config register to go to a high-impedance state when CS is high. If the
ADS1118 does not share the serial bus with another device, CS may be tied low.
CS⁽¹⁾
SCLK
Hi-Z
8 µs
DOUT/DRDY
DIN
(1) CS may be held low. If CS is low, DOUT/DRDY asserts low indicating new data are available.
Figure 43. DOUT/DRDY Behavior Without Data Retrieval in Continuous Conversion Mode
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